hey people
is there any fiber optic connector that enables a simple led to transmit /
receive from
fiber ?
i know there are modules , maybe one know of good low cost modules for 9600bps ,
that works
at low current , with low cost  ?

sincerly yaniv vilnai

Hi Joerg,

--- In buildcheapeeg@y..., "Joerg Hansmann"
<info@j...> wrote:
> This could be a solution. However you lose the
> enhancement of the protection circuit impedance by
> the open loop gain of the input buffer. But you get
> at least a better common mode impedance (what would
> be adequate IMO)

Yes, connecting the transistors to the buffer output
would exhibit least possible leakage, but the
transistors leak very little at low voltages (< 100mV)
so that it may not make much difference?

>> It is supposed to be entirely passive. The
threshold
>> voltage is determined by the transistors alone so I
>> don't see any reason why it should not.
>
> My question was more intended to see, if the
> the whole www.biosemi.com/publications/artikel7.htm
> circuit "eegfig3.gif" works at low voltage.

Well, the only thing I can see is limited by low
voltage is common mode range, but that has nothing to
do with the protection. Can you think of anything
else?

>> I've attached the new attempt.
>> I hope this works better.
>
> R7 will not really protect X1 because the (-) input
> could still be overloaded.

Ahem, you are right. It looks a lot better if the
transistors are connected to the other end of the
resistor (the resistor is supposed to be there
anyway).

>
> For what purpose are the 1nF C's C1..3 ?
> For shunting HF they must be connected to a low-
> impedance node (what they are seemingly not)

<confused> They don't attenuate HF? My intention here
was to let the capacitor act like a short for high
frequencies between a channel and the reference. It
looks good on paper/in simulation. Could you please
clarify a bit why this is so and how?

> I have also attached an input/user protection
> circuit for the INA114 based amplifier:
>
> Worst case current through any port should be
> ca. 40uA.

Please consider using transistors rather than diodes.
See the attached schematic where I've replaced the
diodes with transistors.

The transistors don't not protect the user very well
due to their higher turn-on voltage, but the diodes,
while an effective protection, leak far too much.

BAR42 schottky diodes (Vf = 0.4V supplied with
Simetrix, that's why I used them) leaked 1nA with a
1mV signal. The transistors leak only a fraction of
that, around 2pA. It gets worse when you add an
offset. At 100mV offset the diodes let 100nA through
while the transistors stay at a lower 20pA. Of course,
all these calculations depend somewhat on what
capacitors are used...

I'm beginning to think we would need to measure the
current through the electrodes and have an active
emergency-shutoff...
That is, if we should still aim for FDA/IEC
compliance? I'm leaning towards just putting something
small and simple together now, so that people can get
started writing software as soon as possible. FDA can
perhaps wait a bit... and the paranoid can always
check the amplifiers with a multimeter before
connecting themselves.

> BTW: Do you have an idea how the PSPICE AMB
> equations for OP-amps looks like ? (gain and
> three poles would be enough ...)

Unfortunately no.
I'm guessing here that your spice-simulator lacks
built-in support for opamps? You have previously
mentioned that you were forced to simulate opamps
using voltage controlled voltage sources.

In that case, take a look at Simetrix:
http://www.newburytech.co.uk/

The user interface is a bit different, and the free
version limits circuit size, but other than that, it
is very good.

> It seems to me that this could be done with the
> LAPLACE transform...

If you have plots of the open-loop gain and phase for
an opamp you could try to make a transfer function
from that, but I think it would be a lot of work...

> or is this only for transient analysis ?

Since the laplace-transform was designed for frequency
calculations, it should work fine for AC-analysis as
well.

Regards,

/Andreas

PS

I made a little practical experiment the other day:

I've built some electrodes of 18mm silver discs, and
using two of them I measured the impedance on the
lower arm.

First it was cleaned with alcohol and salt water was
poured onto it. The electrodes (non chloridized, also
cleaned with alcohol) were applied and pressed hard
onto the skin. The resistance was measured with a
multimeter.

The results: 160Kohms when they were about 10 cm apart
and 24Kohm when they were 1 cm apart.

I would have gotten lower values if I had scrubbed the
skin, but when you are supposed to measure EEG on
yourself, that's hard to do to and is not very
comfortable.

DS.

_____________________________________________________
Do You Yahoo!?
se.yahoo.com

Hi Jim,

----- Original Message -----
From: Jim Meissner <jpmeissner@...>
To: <buildcheapeeg@yahoogroups.com>
Sent: Monday, December 31, 2001 6:24 PM
Subject: Re: [buildcheapeeg] Re: Meditation - UP mode


>Dear Joerg:
>
>I would be very interested to see - hear what you have written.

OK. You should have it now in a separate email.
It works with win9x (e.g. Windows 98)

>I am not a programmer but I work at it.  So far as I am aware,
>it is not possible to get accurate microsecond timing when addressing
>the sound card to generate pulses.

At 96kHz sample rate you get 10.4us resolution.

>Maybe you have the answer? ( BTW
>a 10 microsecond difference is significant! )

Speed of sound in air is about 300m/s.

So 10us is equivalent to 3mm runlenght difference. Why should that
be so important when a sound-source is positioned from left to right
and reverse ?

I have experimented with delays up to 1000us and could definitely
not tell the difference between 1000us and 500us. (So maybe I have
problems with my ears ;-) )


>With my Brain State Synchronizer, I use Small "C" and the pulse
>routines are written in machine code to get the speed.
>
>If you have a skeleton of the code that works I would be willing
>to try to fine tune it.

The source is in the separate email too.

Alternatively you could tell me what could be improved and
I implement it.

>Let's see if you got something that works before you worry about
>option 1) or 2) or others.

There is at least some evidence, that it works:

Some days ago I visited a friend who seemingly needed some coffee:
Accidentally at this time an annoying fly was buzzing around him.
He tried about twenty times to catch it and gave up.
After listening to the sound for some minutes, he was able to
get the fly in only two attempts.


Regards,

Joerg

Hi Andreas,

----- Original Message -----
From: Andreas Robinson <sleeper75se@...>
To: <buildcheapeeg@yahoogroups.com>
Sent: Tuesday, January 01, 2002 4:30 PM
Subject: [buildcheapeeg] Re: Input protection


> Hi Joerg,
...
> Well, the only thing I can see is limited by low
> voltage is common mode range, but that has nothing to
> do with the protection. Can you think of anything
> else?

Lowest possible operating voltage of the used OPs.
Are they all rail-to rail ? (Or at least near to that)

...
> > For what purpose are the 1nF C's C1..3 ?
> > For shunting HF they must be connected to a low-
> > impedance node (what they are seemingly not)
>
> <confused> They don't attenuate HF?

Only in differential mode as far as I can see.
However common mode rejection of OPs decreases at high
frequencies. So HF should also be shunted for common mode.


> My intention here
> was to let the capacitor act like a short for high
> frequencies between a channel and the reference. It
> looks good on paper/in simulation.

Also for common mode HF signals ?

...
> Please consider using transistors rather than diodes.
> See the attached schematic where I've replaced the
> diodes with transistors.
> The transistors don't not protect the user very well


A forward voltage of 0.7 V together with the 15k R
would in worst case exceed 50uA. On the other hand
I do not like to increase the 15k significantly
(in combination with INA114).


> due to their higher turn-on voltage, but the diodes,
> while an effective protection, leak far too much.
>
> BAR42 schottky diodes (Vf = 0.4V supplied with
> Simetrix, that's why I used them) leaked 1nA with a
> 1mV signal. The transistors leak only a fraction of
> that, around 2pA. It gets worse when you add an
> offset. At 100mV offset the diodes let 100nA through
> while the transistors stay at a lower 20pA. Of course,
> all these calculations depend somewhat on what
> capacitors are used...


Oops, I did not realize that shottky diodes were so bad.
Are BAT48 diodes(max 40V, 0.35 A) comparable with BAR42
(max 30V,0.1 A)?
I fear they are even worse ...

Do such things like shottky transistors exist ?
(Like in the 74LS- TTL-series)

> I'm beginning to think we would need to measure the
> current through the electrodes and have an active
> emergency-shutoff...

I have had the same idea, but could not find a
way to measure the error-condition without
producing noise, degrading impedance or adding new
risk by the protection circuit.

> That is, if we should still aim for FDA/IEC
> compliance?

At least IEC, because it is easier to comply.

> I'm leaning towards just putting something
> small and simple together now, so that people can get
> started writing software

For writing SW the digital part would be enough.

> as soon as possible. FDA can
> perhaps wait a bit... and the paranoid can always
> check the amplifiers with a multimeter before
> connecting themselves.
>
> > BTW: Do you have an idea how the PSPICE AMB
> > equations for OP-amps looks like ? (gain and
> > three poles would be enough ...)
>
> Unfortunately no.
> I'm guessing here that your spice-simulator lacks
> built-in support for opamps?

It is restricted (freeware version) to 3 real op-amps
simulated on transistor level or 50 parts over all.

> You have previously
> mentioned that you were forced to simulate opamps
> using voltage controlled voltage sources.

Yes, it is a more or less accurate work-around.

> In that case, take a look at Simetrix:
> http://www.newburytech.co.uk/
>
> The user interface is a bit different, and the free
> version limits circuit size, but other than that, it
> is very good.

I will have a look at it. (At the moment I am trying switchercad,
a free and _unlimited_ PSPICE. See addendum for more)

...
> I made a little practical experiment the other day:
>
> I've built some electrodes of 18mm silver discs, and
> using two of them I measured the impedance on the
> lower arm.
>
> First it was cleaned with alcohol and salt water was
> poured onto it.

A kind of sponge or cellulose tissue that is soaked with the
saline would be better I assume.

> The electrodes (non chloridized, also
> cleaned with alcohol) were applied and pressed hard
> onto the skin. The resistance was measured with a
> multimeter.

Normal multimeters use DC current to measure resistance.
This quickly produces a galvanic reaction (like loading a
battery) and falsifies the reading.


> The results: 160Kohms when they were about 10 cm apart
> and 24Kohm when they were 1 cm apart.

Hmmm. the distance should not matter, because the transitional
resistance of the skin to the body internal normally is much higher
than the resistance of the internal.

> I would have gotten lower values

Perhaps you should use 10/20 paste wax...

Regards,

Joerg


BTW: I am just testing this here:
(could be a good alternative to my limited microsim eval version)

SwitcherCAD III
---------------
Free, high-performance, unlimited, fully functional
SPICE simulator with integrated schematic capture and waveform
viewer:

"...
This program will run all those Pspice models in public
domain or available from vender sites, but faster and
more reliably than Pspice.  Somehow I've gotten the vague
impression that there is no one working full time on SPICE
internals for Pspice, not that I have any inside
information at all or am in any way connected with
MicroSim/OrCAD/Cadence.  Maybe Mohi who posts here
from his Cadence address can verify.

Version 1.10h is available for immediate download(save
possible site mirroring delays) as

   http://LTspice.linear-tech.com/software/swcadiii.exe

People with earlier versions installed can use the "Tools=>Sync
Release" menu option to incrementally update to the current
version and bypass all site mirroring.

This is a free, high-performance, unlimited, fully functional
SPICE simulator with integrated schematic capture and waveform
viewer.  It is not shareware or a demo. It is a fully functional
freeware.

   * P-SPICE compatible semiconductors models, e.g.:
       - diode recombination current
       - bipolar quasi saturation
       - JFET impact ionization
   * P-SPICE behavioral modeling, both legacy POLY() statements
     and arbitrary expressions, Laplace, and look-up tables.
   * P-SPICE netlist compatibility for .param, .func, ako models...
   * New devices such as an arbitrary capacitance.  Write an
     expression for the charge, it symbolically differentiates the
     expression and integrates the capacitances.  I've found it
     useful for doing rapid prototyping of hypothetical transistor
     behavior.
   * An original mixed mode simulator(not xspice based)
   * A VDMOS transistor device that intrinsically handles the
     power MOSFET's gate charge behavior
   * BSIM 3.2.2, BSIM 4.1, BSIMPD2.2, and EKV 2.6
   * Marching waveforms/cross probing of any device or subcircuit
     port current
   * Dynamic waveform data compression
   * Device library/database(power MOSFETs, diodes, bipolars, JFETS)
   * 350+ models of switch mode controllers
   * Integrated schematic capture with unlimited undo and redo
   * Parametric plotting(often called X-Y plotting)
   * Fourier analysis(both .four statements and FFT's of simulated
     data.)
   * Numerous educational example circuits included.
   * Free lifetime updates

This is a very easy to use SPICE/Schematic capture system.  It
includes clear, on-line help but you should just be able to
mouse it out without reading any documentation.  You draft your
circuit and push the "Run" toolbar button.  There are numerous
examples included in the "examples\Educational" directory.

It is the World's fastest SPICE.  It started out as a re-write
of Berkeley SPICE 3F4/5 to improve it's performance on machines
with faster processors than memory and to improve the timestep
control of Berkeley SPICE.  Analog design engineers use it for
full-chip, transistor level simulations.  Typical speed-ups
over P-SPICE 9.1 are three to six fold.  It wins the industry
standard transistor-level SPICE bench mark, the MCNC Bench Mark
Suite, in speed and convergence.  Of course, when using it's
own mixed-mode simulator in it's own native HDL, there's
nothing like it at all.  There's been articles appearing, e.g.,
the June 18th Electronic Design[1] and there are advertisements
in various current trade journals.  It's called SwitcherCAD III
and you can download it from www.linear-tech.com/software/.
..."

THis year, I hired two artists to design a logo for the Futurehealth Winter
Brain meeting.

I gave them the theme:

New World / New Brain

They came up with a number of ideas, and I am trying to sort out which is
the best.

I've posted a batch of them to both the yahoogroups.com website
underhttp://photos.groups.yahoo.com/group/biofbp/lst
If you go here, you may have to sign on the the Biofbp listserve, if you
are not already subscribed. If you prefer not to, you can go  my website,
at www.futurehealth.org/2002.htm.

The yahoo site has better images, and will allow you to view a slideshow,
if you click on the word slideshow. The Futurehealth site has been newly
updated with a lot more speaker information,l and images of most of the
speakers.

Then, please either reply to this e-mail with your first and second choice
and your comments, or use the poll I created at the yahoo biofbp website.

Thanks,

Rob Kall

I'd like your feedback on which you like best and why.




Rob Kall
Futurehealth, Inc.
211 N. Sycamore St., Newtown, PA 18940  215-504-1700, fax 215-860-5374

10th annual  Winter Brain Meeting  www.futurehealth.org/2002.htm  February
7-11, Miami Florida

When you are involved with other human beings, the work on yourself is a
critical part of your gift to the other person.
Ram Dass, 1996, lecture on Conscious Aging

Enlarge your consciousness.  If your consciousness is small, you will
experience smallness in every department of your life.
      Robert Pante
www.storyscience.com
Storycon World's First Conference on the Science Art and Application of
Story

BioFbP  Listserve. The Listserve For Biofeedback Practitioners.
Subscribe:  biofbp-subscribe@yahoogroups.com

----- Original Message -----

From: Joerg Hansmann

To: buildcheapeeg@yahoogroups.com

Sent: Tuesday, January 01, 2002 12:08 PM

Subject: Re: [buildcheapeeg] Re: Meditation - UP mode

Hi Jim,

----- Original Message -----
From: Jim Meissner <jpmeissner@...>
To: <buildcheapeeg@yahoogroups.com>
Sent: Monday, December 31, 2001 6:24 PM
Subject: Re: [buildcheapeeg] Re: Meditation - UP mode


>Dear Joerg:
>
>I would be very interested to see - hear what you have written.

OK. You should have it now in a separate email.
It works with win9x (e.g. Windows 98)

>I am not a programmer but I work at it.  So far as I am aware,
>it is not possible to get accurate microsecond timing when addressing
>the sound card to generate pulses.

At 96kHz sample rate you get 10.4us resolution.

>Maybe you have the answer? ( BTW
>a 10 microsecond difference is significant! )

Speed of sound in air is about 300m/s.

So 10us is equivalent to 3mm runlenght difference. Why should that
be so important when a sound-source is positioned from left to right
and reverse ?

I have experimented with delays up to 1000us and could definitely
not tell the difference between 1000us and 500us. (So maybe I have
problems with my ears ;-) )


>With my Brain State Synchronizer, I use Small "C" and the pulse
>routines are written in machine code to get the speed.
> 
>If you have a skeleton of the code that works I would be willing
>to try to fine tune it.

The source is in the separate email too.

Alternatively you could tell me what could be improved and
I implement it.

>Let's see if you got something that works before you worry about
>option 1) or 2) or others.

There is at least some evidence, that it works:

Some days ago I visited a friend who seemingly needed some coffee:
Accidentally at this time an annoying fly was buzzing around him.
He tried about twenty times to catch it and gave up.
After listening to the sound for some minutes, he was able to
get the fly in only two attempts.


Regards,

Joerg












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buildcheapeeg-unsubscribe@egroups.com



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hi
the ir option you just mentioned , sounds like a great soultion to the isolation
problem .
tell me , what was the distance between the 2 boards (bm , and isolation card )
?
could it be one meter at 9600 baud ?

thanks yaniv

--- In buildcheapeeg@y..., "Brian Gr" <brian_gr@h...> wrote:
> Hi,
> I built a BrainMaster when it was an open design. I went through similar
issues with power
and isolation. Here's what I did with the bm, maybe they could be of some use in
this design:
>
> I put only one connector on the unit, a 25 pin D connector. Depending on which
of two
cables were plugged into this unit, one could either operate the unit or charge
the internal
6 nicads in the unit, but one couldn't run the unit with the charger, at least
with these
connectors.
>
> The nicads were connected to the 25 pin D connector in 3 battery pairs. The
eeg inputs
were connected to the 25 pin D connector. The input and ground and isolated
serial was
connected to this connetor as well.
>
> One D connector/circuit was used to charge the batteries. It connected a wall
wart to a
couple of resistors to charge the internal batteries. You couldn't operate the
unit when
this connector was connected as the rs232 and eeg inputs were not connected on
this
connector/circuit.
>
> A second connector/circuit was used to operate the unit. By connecting pins on
this
connector,  the three pairs of batteries were connected in series and fed to a
voltage in
and ground pin on the 25 pin connector. This powered the unit. This connector
had eeg inputs
and ref ground and isolated rs232 connected as well.
>
> The Vin and ground were available on the connector, so I suppose someone could
or would
think of connecting an unisolated supply to this input and not using the
internal batteries.
Well, I'm no dummy, I never would.
>
> To isolate rs232, I used 2 pairs of ir leds and integral ir recievers from
Digikey. They
were Fairchild parts. Current Digikey part #s are QSE158-ND ($1.42, qty 1)
(http://rocky.digikey.com/scripts/ProductInfo.dll?Site=CA&V=46&M=QSE158) for the
logic
detector and QEE113-ND ($.74, qty 1)
(http://rocky.digikey.com/scripts/ProductInfo.dll?
Site=CA&V=46&M=QEE113) for the ir diode. The reciever has built in circuitry to
generate
logic out from IR in. The leds and current limiting resistor were connected to
the tx on
both sides and the logic detector was connected to the rx on both sides.
Pointing the
appropriate led / detector pair at each other allowed isolation. The BM board
had one pair
and the isolation board had another pair. You might think of these as
optoisolators in two
packages. You could control the distance between the pairs to increase
isolation. There was
no problem running 9600 baud across these parts.
>
> If I was  to build this again, I would put a seperate connector for the
isolated RS232 to
increase the distance between the isolated and non isolated portions of the
circuitry. On my
brainmaster, the isolated and non isolated circuits go to the same connector,
with a couple
of blank pins between.
>
> Brian.

Dear Jim,

----- Original Message -----
From: Jim Meissner <jpmeissner@...>
To: <buildcheapeeg@yahoogroups.com>
Sent: Wednesday, January 02, 2002 4:07 AM
Subject: Re: [buildcheapeeg] Re: Meditation - UP mode

...
> > At 96kHz sample rate you get 10.4us resolution.
>
> Does that mean that at 44100 it would be 20.8 us?

Yes.

> That might be a bit jerky
> but maybe OK, I would have to hear it.

Hopefully I will have a SDL console application (with command line interpreter)
running the next days. Then it should be possible to play around with all
parameters without recompiling.

> > I have experimented with delays up to 1000us and could definitely
> > not tell the difference between 1000us and 500us. (So maybe I have
> > problems with my ears ;-) )
>
> I would not have believed that a biological system could respond to even
> millisecond delays. I was shocked when I discovered this. Try it again with
> two identical 3 msec. pulses. Shift
> the phase by 100 us and you will be surprised how sensitive the ear/brain
> system is to establishing the apparent direction.

Seemingly not my...
Without attenuating the delayed channel by at least 6dB,
delay alone only gives me a very vague direction impression.

> This sense has kept man alive for thousands of years. A large part of the
> brain is devoted to keeping track of his sonic environment.

Perhaps thousands of years ago I would have had no chance to survive ;-)

> > If you have a skeleton of the code that works I would be willing
> > to try to fine tune it.
> > The source is in the separate email too.
> > Alternatively you could tell me what could be improved and
> > I implement it.
>
> I was able to get your program to run. Nice job.
> Even though the frequencies went from 10 to 20 hz,

Should it have been another range for UP-Mode PROG 01 ?

> I found it
> very annoying to listen to.

I am confused: Is this good or bad ?

> Much of the programming of the sound sequence is art.
> I spent months fine tuning the
> frequencies. My joke is that Jimmy Hendrix and Andre Segovia
> both played the guitar, but what a difference.

Thanks, I needed that ;-)
Now I only have to guess, who I am...

> I looked at your code and will need a few hours to study it.
> If I am able to remember how to program in C, I would
> prefer to modify the code on my computer and do the fine
> tuning here.

Feel free to do that. However the code is under
construction and changes rapidly.

> Would you be willing to set me up with the
> programs needed to compile the C code and run it here?

I have used the MSVC6.0 compiler and can give you the
project files (*.dsw, *.dsp).
Everything else (SDL 1.2.3) can be downloaded at http://www.libsdl.org

If you do not have MSVC and want a freeware compiler instead, it should be
possible to use the GNU mingw32 compiler. However I do not have any
experience with mingw32.

> I have a Compaq Presario 1250,

CPU ? Mhz ? RAM ?
Soundcard ?

> with Win98.

Should be OK.

> Years ago I hired a programmer to write the core program and then
> I was able to push variables around until it
> sounded "right". There are about 12 variables that control all
> the programs in my Brain State Synchronizer. These
> are called up from the EPROM and loaded into the program and
> run.


The version currently under construction has 17 parameters:

/*
SweepDuration_sec;
PulseLength_sec;

// frequency sweep:
// ----------------
StartFreq_Hz;
StartFreqRnd_Hz;    // +- random frequency modulation per pulse
EndFreq_Hz;
EndFreqRnd_Hz;      // +- random frequency modulation per pulse

// stereo position sweep:
// ----------------------
StartPosition;      // -1.0 max left, 0 middle, +1.0 max right
StartPositionRnd;   // +- random per pulse
EndPosition;        // -1.0 max left, 0 middle, +1.0 max right
EndPositionRnd;     // +- random per pulse
MaxAttenuation_dB;
MaxDelay_sec;

// volume sweep:
// -------------
StartVolume_dB;
StartVolumeRnd_dB;  // +- random amplitude modulation per pulse
EndVolume_dB;
EndVolumeRnd_dB;    // +- random amplitude modulation per pulse

// misc:
// -----
next_to_do;         // 0: repeat forever, -1: stop, n>0: load parameter set n
*/


So I guess, that I change things, that were fixed in your SW ?

> On the PC these could be in a BAT file that
> the program looks at and executes. During development it would
> be nice to have an on screen edit of the variables,
> and then to save that to a file for future use.

I am just working on that (using SDL_console package)

> What do you think?

Yes. Why not. It could be done that way.


Regards,

Joerg

Hi Brian,

do you know what the BM have for ESD-protecting the electrode inputs?
Also, is there any kind of user protection if the input amplifiers
get shorted to the power supply?

Be well,

Andreas

Hi Joerg,

--- In buildcheapeeg@y..., "Joerg Hansmann" <info@j...> wrote:
> Lowest possible operating voltage of the used OPs.
> Are they all rail-to rail ? (Or at least near to that)

Ah, now I understand. Ok, the datasheet for LT1012 says this:

Minimum supply voltage: +/-1.2 volts
CM-range: typically V+ - 0.9V and V- + 0.9V
So powering it at +/- 2.5V would give you a common mode range of +/-
1.6V.
CMRR is 40dB at 1MHz, falling about 20dB per decade, by the way.
It is not rail-to-rail, at +/-15V supply voltage the swing is
characterized to typically +/- 14V. I don't know how that scales, but
a wild guess is +/- 1.5V at 2.5V supply voltage.

> Only in differential mode as far as I can see.
> However common mode rejection of OPs decreases at high
> frequencies. So HF should also be shunted for common mode.

Yes, you are right, it does not attenuate the HF common mode signals,
but one could argue that those are not amplified either...

Of course, better safe than sorry, but isn't it hard to get the the
ground/shield quiet enough for what is essentially a HF short-circuit
to the most sensitive, high-impedance part of the system?

Hmm, I think we have reached the point where we need to build and
test.

> Oops, I did not realize that shottky diodes were so bad.
> Are BAT48 diodes(max 40V, 0.35 A) comparable with BAR42
> (max 30V,0.1 A)?
> I fear they are even worse ...

Unfortunately I was unable to find a model for BAT48 and the data
sheet only characterized the reverse leakage at 10V and up... (2uA)

>
> Do such things like shottky transistors exist ?
> (Like in the 74LS- TTL-series)

I have never heard of that... Hmm, question is if they wouldn't leak
as much as a diode. Part of the regular bipolar transistors low
leakage (and poor user-protection) could depend on the high turn-on
voltage. (0.7V)

> > I'm beginning to think we would need to measure the
> > current through the electrodes and have an active
> > emergency-shutoff...
>
> I have had the same idea, but could not find a
> way to measure the error-condition without
> producing noise, degrading impedance or adding new
> risk by the protection circuit.

A differential amplifier built from two N-channel MOSFETS measuring
the voltage drop across a resistor, would that work? They are nice
and quiet AFAIK. Since the amplifier would be discrete, we could
limit the drain-source current using large resistors (100K+) and keep
the user safe. Noise would not be that important if the system
averages the measurement over perhaps 100ms. A high overcurrent would
trigger the shut-off circuitry faster than an overcurrent that is
only a little bit over the limit.

Hmm, I think I'll read up on MOSFETS...

> > In that case, take a look at Simetrix:
> > http://www.newburytech.co.uk/
> >
> > The user interface is a bit different, and the free
> > version limits circuit size, but other than that, it
> > is very good.
>
> I will have a look at it. (At the moment I am trying switchercad,
> a free and _unlimited_ PSPICE. See addendum for more)

I read the addendum. Just ignore my suggesting Simetrix. :-)
I have not installed SwitcherCAD yet, but an unlimited version is
always better than any limited one, if it is user-friendly enough.

> > I made a little practical experiment the other day:
[snip]
> > The results: 160Kohms when they were about 10 cm apart
> > and 24Kohm when they were 1 cm apart.
>
> Hmmm. the distance should not matter, because the transitional
> resistance of the skin to the body internal normally is much higher
> than the resistance of the internal.

Perhaps I was measuring the resistance of the saline solution on the
surface of the skin ...

Anyway, when the electrodes are finished, I'll hook myself up to a
prototype EEG and do a real test with everything done properly.

Regards,

Andreas

----- Original Message -----

From: Joerg Hansmann

To: buildcheapeeg@yahoogroups.com

Sent: Wednesday, January 02, 2002 1:27 PM

Subject: Re: [buildcheapeeg] Re: Meditation - UP mode

Dear Jim,

----- Original Message -----
From: Jim Meissner <jpmeissner@...>
To: <buildcheapeeg@yahoogroups.com>
Sent: Wednesday, January 02, 2002 4:07 AM
Subject: Re: [buildcheapeeg] Re: Meditation - UP mode

...
> > At 96kHz sample rate you get 10.4us resolution.
>
> Does that mean that at 44100 it would be 20.8 us?

Yes.

> That might be a bit jerky
> but maybe OK, I would have to hear it.

Hopefully I will have a SDL console application (with command line interpreter)
running the next days. Then it should be possible to play around with all
parameters without recompiling. 

> > I have experimented with delays up to 1000us and could definitely
> > not tell the difference between 1000us and 500us. (So maybe I have
> > problems with my ears ;-) )
>
> I would not have believed that a biological system could respond to even
> millisecond delays. I was shocked when I discovered this. Try it again with
> two identical 3 msec. pulses. Shift
> the phase by 100 us and you will be surprised how sensitive the ear/brain
> system is to establishing the apparent direction.

Seemingly not my...
Without attenuating the delayed channel by at least 6dB,
delay alone only gives me a very vague direction impression.

> This sense has kept man alive for thousands of years. A large part of the
> brain is devoted to keeping track of his sonic environment.

Perhaps thousands of years ago I would have had no chance to survive ;-)

> > If you have a skeleton of the code that works I would be willing
> > to try to fine tune it.
> > The source is in the separate email too.
> > Alternatively you could tell me what could be improved and
> > I implement it.
>
> I was able to get your program to run. Nice job.
> Even though the frequencies went from 10 to 20 hz,

Should it have been another range for UP-Mode PROG 01 ?

> I found it
> very annoying to listen to.

I am confused: Is this good or bad ?

> Much of the programming of the sound sequence is art.
> I spent months fine tuning the
> frequencies. My joke is that Jimmy Hendrix and Andre Segovia
> both played the guitar, but what a difference.

Thanks, I needed that ;-)
Now I only have to guess, who I am...

> I looked at your code and will need a few hours to study it.
> If I am able to remember how to program in C, I would
> prefer to modify the code on my computer and do the fine
> tuning here.

Feel free to do that. However the code is under
construction and changes rapidly.

> Would you be willing to set me up with the
> programs needed to compile the C code and run it here?

I have used the MSVC6.0 compiler and can give you the
project files (*.dsw, *.dsp).
Everything else (SDL 1.2.3) can be downloaded at http://www.libsdl.org

If you do not have MSVC and want a freeware compiler instead, it should be
possible to use the GNU mingw32 compiler. However I do not have any
experience with mingw32.

> I have a Compaq Presario 1250,

CPU ? Mhz ? RAM ?
Soundcard ?

> with Win98.

Should be OK.

> Years ago I hired a programmer to write the core program and then
> I was able to push variables around until it
> sounded "right". There are about 12 variables that control all
> the programs in my Brain State Synchronizer. These
> are called up from the EPROM and loaded into the program and
> run.


The version currently under construction has 17 parameters:

/*
SweepDuration_sec;
PulseLength_sec;

// frequency sweep:
// ----------------
StartFreq_Hz;
StartFreqRnd_Hz;    // +- random frequency modulation per pulse
EndFreq_Hz;
EndFreqRnd_Hz;      // +- random frequency modulation per pulse

// stereo position sweep:
// ----------------------
StartPosition;      // -1.0 max left, 0 middle, +1.0 max right
StartPositionRnd;   // +- random per pulse
EndPosition;        // -1.0 max left, 0 middle, +1.0 max right
EndPositionRnd;     // +- random per pulse
MaxAttenuation_dB;
MaxDelay_sec;

// volume sweep:
// -------------
StartVolume_dB;
StartVolumeRnd_dB;  // +- random amplitude modulation per pulse
EndVolume_dB;
EndVolumeRnd_dB;    // +- random amplitude modulation per pulse

// misc:
// -----
next_to_do;         // 0: repeat forever, -1: stop, n>0: load parameter set n
*/


So I guess, that I change things, that were fixed in your SW ?

> On the PC these could be in a BAT file that
> the program looks at and executes. During development it would
> be nice to have an on screen edit of the variables,
> and then to save that to a file for future use.

I am just working on that (using SDL_console package)

> What do you think?

Yes. Why not. It could be done that way.


Regards,

Joerg


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Dear Jim,

----- Original Message -----
From: Jim Meissner <jpmeissner@...>
To: <buildcheapeeg@yahoogroups.com>
Sent: Thursday, January 03, 2002 12:01 AM
Subject: Re: [buildcheapeeg] Re: Meditation - UP mode


...
> I did not look at the sound with the oscilloscope yet, but the phase
> was all over the place.  I do not know if you did that on purpose or not.
> I did not like to listen to it....

The (phase) delay was 400us. Also there was an additional
random amplitude modulation. :

void InitUserData(void){
   Prog01.PulseLength_sec=0.003;
   Prog01.StartFreq=10.0;
   Prog01.EndFreq=20.0;
   Prog01.SweepDuration_sec=3*60;
   Prog01.Delay_sec=400e-6;//400e-6;
   Prog01.Volume_dB=0; // not yet implemented
   Prog01.Attenuation_dB=-6;//-20;
};


> Could you write a version with no delays and rand() functions to
> see if the pulses were working.  Just equal pulses that sound centered.

Ok.

I have set all random parameters and delay to 0:

void InitUserData(void){
   Prog01.PulseLength_sec=0.003;
   Prog01.StartFreq=10.0;
   Prog01.EndFreq=20.0;
   Prog01.RandomFreqVariation=0.0;//+- random range added to frequency sweep
   Prog01.SweepDuration_sec=3*60;
   Prog01.Delay_sec=00e-6;//400e-6;
   Prog01.Volume_dB=0; // not yet implemented
   Prog01.Attenuation_dB=0;//-6;//-20;
};



The *.exe (zipped, 3.85 KB) is in the attachment.
Just copy/extract it over your previous exe-file.


> I am studying your code.  I have never used structures before.

Structures are just a handy way to keep data together by defining
a new datatype (e.g. struct TSoundParameter) and some instances of this
new datatype (e.g. Prog01).

If you have a pointer to the structure, you can access the data with the
"->" operator. If you have an instance (also called variable) of the
structure, you access the data with the "." operator.
...

Regards,

   Joerg

----- Original Message -----

From: Joerg Hansmann

To: buildcheapeeg@yahoogroups.com

Sent: Wednesday, January 02, 2002 7:14 PM

Subject: Re: [buildcheapeeg] Re: Meditation - UP mode

Dear Jim,

----- Original Message -----
From: Jim Meissner <jpmeissner@...>
To: <buildcheapeeg@yahoogroups.com>
Sent: Thursday, January 03, 2002 12:01 AM
Subject: Re: [buildcheapeeg] Re: Meditation - UP mode


...
> I did not look at the sound with the oscilloscope yet, but the phase
> was all over the place.  I do not know if you did that on purpose or not.
> I did not like to listen to it....

The (phase) delay was 400us. Also there was an additional
random amplitude modulation. :

void InitUserData(void){
  Prog01.PulseLength_sec=0.003;
  Prog01.StartFreq=10.0;
  Prog01.EndFreq=20.0;
  Prog01.SweepDuration_sec=3*60;
  Prog01.Delay_sec=400e-6;//400e-6;
  Prog01.Volume_dB=0; // not yet implemented
  Prog01.Attenuation_dB=-6;//-20;
};


> Could you write a version with no delays and rand() functions to
> see if the pulses were working.  Just equal pulses that sound centered.

Ok.

I have set all random parameters and delay to 0:

void InitUserData(void){
  Prog01.PulseLength_sec=0.003;
  Prog01.StartFreq=10.0;
  Prog01.EndFreq=20.0;
  Prog01.RandomFreqVariation=0.0;//+- random range added to frequency sweep
  Prog01.SweepDuration_sec=3*60;
  Prog01.Delay_sec=00e-6;//400e-6;
  Prog01.Volume_dB=0; // not yet implemented
  Prog01.Attenuation_dB=0;//-6;//-20;
};



The *.exe (zipped, 3.85 KB) is in the attachment.
Just copy/extract it over your previous exe-file.


> I am studying your code.  I have never used structures before.

Structures are just a handy way to keep data together by defining
a new datatype (e.g. struct TSoundParameter) and some instances of this
new datatype (e.g. Prog01).

If you have a pointer to the structure, you can access the data with the
"->" operator. If you have an instance (also called variable) of the
structure, you access the data with the "." operator.
...

Regards,

  Joerg



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buildcheapeeg-unsubscribe@egroups.com



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----- Original Message -----

From: sleeper75se

To: buildcheapeeg@yahoogroups.com

Sent: Wednesday, January 02, 2002 2:47 PM

Subject: [buildcheapeeg] Re: Power/isolation issues...bm solution

Hi Brian,

do you know what the BM have for ESD-protecting the electrode inputs?
Also, is there any kind of user protection if the input amplifiers
get shorted to the power supply?

Be well,

Andreas




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--- In buildcheapeeg@y..., "Brian Gr" <brian_gr@h...> wrote:
> I don't have the BM schematics here but if memory serves
> correct, their wasn't any ESD protection on the input stage.
> The electrode inputs were connected to the instrumentation
> amplifiers (AD621 I believe) via 10 Meg resistors, so that
> would significantly limit any current in event of AD621
> catastrophic failure and possibly provide some ESD protection.

It turns out the old BM was connected to the user via .01uf
_caps_, and the 10M resistors were only across the AD620 inputs
to ground.

Also, I have it on good authority that the current BM that
they sell is _not_, however, like that published circuit, and
has an input impedance of 5 gigohms, and thus likely also has
some nice fancy input protection.

- Lenny Gray -

----- Original Message -----

From: Brian Gr

To: buildcheapeeg@yahoogroups.com

Sent: Saturday, December 29, 2001 8:57 PM

Subject: [buildcheapeeg] Power/isolation issues...bm solution

Hi,

I built a BrainMaster when it was an open design. I went through similar issues with power and isolation. Here's what I did with the bm, maybe they could be of some use in this design:

 

I put only one connector on the unit, a 25 pin D connector. Depending on which of two cables were plugged into this unit, one could either operate the unit or charge the internal 6 nicads in the unit, but one couldn't run the unit with the charger, at least with these connectors.

 

The nicads were connected to the 25 pin D connector in 3 battery pairs. The eeg inputs were connected to the 25 pin D connector. The input and ground and isolated serial was connected to this connetor as well.

 

One D connector/circuit was used to charge the batteries. It connected a wall wart to a couple of resistors to charge the internal batteries. You couldn't operate the unit when this connector was connected as the rs232 and eeg inputs were not connected on this connector/circuit.

 

A second connector/circuit was used to operate the unit. By connecting pins on this connector,  the three pairs of batteries were connected in series and fed to a voltage in and ground pin on the 25 pin connector. This powered the unit. This connector had eeg inputs and ref ground and isolated rs232 connected as well.

 

The Vin and ground were available on the connector, so I suppose someone could or would think of connecting an unisolated supply to this input and not using the internal batteries. Well, I'm no dummy, I never would.

 

To isolate rs232, I used 2 pairs of ir leds and integral ir recievers from Digikey. They were Fairchild parts. Current Digikey part #s are QSE158-ND ($1.42, qty 1)(http://rocky.digikey.com/scripts/ProductInfo.dll?Site=CA&V=46&M=QSE158) for the logic detector and QEE113-ND ($.74, qty 1) (http://rocky.digikey.com/scripts/ProductInfo.dll?Site=CA&V=46&M=QEE113) for the ir diode. The reciever has built in circuitry to generate logic out from IR in. The leds and current limiting resistor were connected to the tx on both sides and the logic detector was connected to the rx on both sides. Pointing the appropriate led / detector pair at each other allowed isolation. The BM board had one pair and the isolation board had another pair. You might think of these as optoisolators in two packages. You could control the distance between the pairs to increase isolation. There was no problem running 9600 baud across these parts.

 

If I was  to build this again, I would put a seperate connector for the isolated RS232 to increase the distance between the isolated and non isolated portions of the circuitry. On my brainmaster, the isolated and non isolated circuits go to the same connector, with a couple of blank pins between.

 

Brian.

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Hi,
I would like to build or buy a cheap biofeedback device. I am
considering building either Hansman's EEG_rs232_01_000905 or the
modular EEG biofeedback. I am not sure if these designs are final and
fully functional and what software for training could I use with
these devices. Are they compatible with ElectricGuru or BrainMater
1.7A that I have downloaded?
I know that EEG_rs232 should be compatible with ElectricGuru but what
about  BrainMater 1.7A? What is the compatibility of modular EEG I
don't know at all. Is there any other available software for
training
with these devices? I found cheap EEG biofeedback device that is
being sold in Czech Republic in both home (one channel) and clinical
(two channel) version. The home version for less than 400$. The
software seems to be even better for training than the BrainMaster
software. What discourages me from buying is that it is using the
soundcard line-in input. I think that for these low frequencies it is
not a good idea because of the huge signal fall off. I called the
supplier and asked about this issue and I was told that it
doesn't
matter at this design, because it uses rate of increase/decrease at
desired frequencies during training. I am not sure about this. If
anyone is interested in this idea, you can look at the screenshots
and description (unfortunately in Czech only) at
http://www.harmoniabiofeedback.com/Silmaril%20mini/Hry.htm ,
http://www.harmoniabiofeedback.com/Silmaril/start1.htm#3urovnova_stimu
lace , http://www.harmoniabiofeedback.com/Silmaril/prehled1.htm .
  I would appreciate any advice. Thanks a lot. Mike.

hi
does anybody knows the details of the brainmaster communication protocol ?
if so please post it here .
maybe it can be usefull for something .
also if i want to get just the brainmaster software for free , is it possible or
i have to buy the device .

sincerly
yaniv vilnai

hey

here's the protocol of BM .  might be usefull .

again , does anybody have there software  ?

  Note: forwarded message attached.

----- Original Message -----

From: yaniv vilnai

To: Rob Sacks

Sent: Friday, January 04, 2002 3:04 AM

Subject: hi rob

hi rob .

how's life ?

i have a question to ask you : maybe you know the details of the brainmaster communication protocol ?

if so please send them .

also do you know if i can get the bm osftware without buying the device ?

sincerly yaniv v.

p.s. about our status - modular eeg 2-6 channels , low cost , iec certified , i think is in the last stages .

also we trying to find a volunteering lawyer to establish ngo in the states .

 

---

Do You Yahoo!?
Send your FREE holiday greetings online at Yahoo! Greetings.

***** BM_11.ASM ************************************************
* ADC + Digital Input and Output Module for Brain Master Projcet
* Lead by Thomas F. Collura Ph.D., P.E.
*
* Written by and (c) W. Robert S. Webber Ph.D. CEng. MIEE
*
* Squarey Basement Software
*
* Date Wed  6 Sept  1995
*
* Copyright ========================================================
*
* As with any freeware I would make no guarantee, warranty implied or
* otherwise that the code is good for anything, will not harm anyone
* however used. That is, what ever happens or does not happen as a
* result of using or not using this code is not my fault or
* responsibility.
*
* This program is licensed to Tom Collura and the Brain Master
* project to be freely distributed as part of that project.
*
* Any derived work would be the property and responsibility of the
* person deriving such work. An acknowledgement of the original
* source would be appreciated.
*
* =================================================================

* Start of Genaral stuff

* From BUF32.ASM
***************
*   EQUATES   *
***************
RAMBS    EQU  $0000        start of ram

REGBS    EQU  $1000        start of registers

ROMBS    EQU  $E000        start of rom

STREE    EQU  $B600        start of eeprom
ENDEE    EQU  $B7FF        end of eeprom

PORTE    EQU  REGBS+$0A    port E
CFORC    EQU  REGBS+$0B    force output compare
TCNT     EQU  REGBS+$0E    timer count
TOC5     EQU  REGBS+$1E    oc5 reg

TCTL1    EQU  REGBS+$20    timer control 1
TMSK1    EQU  REGBS+$22    timer mask 1
TFLG1    EQU  REGBS+$23    timer flag 1
TMSK2    EQU  REGBS+$24    timer mask 2

BAUD     EQU  REGBS+$2B    sci baud reg
SCCR1    EQU  REGBS+$2C    sci control1 reg
SCCR2    EQU  REGBS+$2D    sci control2 reg
SCSR     EQU  REGBS+$2E    sci status reg
SCDAT    EQU  REGBS+$2F    sci data reg

BPROT    EQU  REGBS+$35    block protect reg
OPTION   EQU  REGBS+$39    option reg
COPRST   EQU  REGBS+$3A    cop reset reg
PPROG    EQU  REGBS+$3B    ee prog reg
HPRIO    EQU  REGBS+$3C    hprio reg

CONFIG    EQU  REGBS+$3F    config register

DFLOP    EQU  $4000    evb d flip flop

DUART    EQU  $D000    duart address
PORTA    EQU  DUART
PORTB    EQU  DUART+8

ACIA    EQU  $9800    acia address

PROMPT    EQU  '>'
BUFFLNG EQU  35
CTLA    EQU  $01    exit host or assembler
CTLB    EQU  $02    send break to host
CTLW    EQU  $17    wait
CTLX    EQU  $18    abort
DEL     EQU  $7F    abort
EOT     EQU  $04    end of text/table
SWI     EQU  $3F

* End of section from BUF32.ASM

BUFISIT   EQU  $e00A  * Cold Start for Buffalo after testing PE0

TMP1      EQU  $00C0  * For Buffalo for use with .HEXBIN
SHFTREG   EQU  $009C  * For Buffalo for use with .HEXBIN
SHFTREG2  EQU  $009D  * For Buffalo for use with .HEXBIN

CTLQ    EQU  $11    * Ctrl/Q Restart i.e. DC1
CTLS    EQU  $13    * Ctrl/S
CTLV    EQU  $16    * Used instead of Ctrl/S for Pause
CTLD    EQU  $04    * Ctrl/D Stop Interrupts & Return to Buffalo
CR_KEY  EQU  $0D    * Carridge Return

TFLG2   EQU REGBS+$25     Timer Flag 2
PACTL   EQU REGBS+$26     Pulse Accumulator Control Reg

PORT_A  EQU REGBS+$00     I/O Port A
PORT_B  EQU REGBS+$04     I/O Port B
PORT_C  EQU REGBS+$03     I/O Port C
PORT_D  EQU REGBS+$08     I/O Port D
PORT_E  EQU REGBS+$0A     I/O Port E

PIOC    EQU REGBS+$02      STAF STAI CWOM HNDS OIN PLS EGA INVB
PORTCTL EQU REGBS+$05
DDRC    EQU REGBS+$07
DDRD    EQU REGBS+$09

* ADC Registers
ADCTL   EQU REGBS+$30   ADC Control Register
ADC_R1  EQU REGBS+$31   ADC Result 1
ADC_R2  EQU REGBS+$32   ADC Result 2
ADC_R3  EQU REGBS+$33   ADC Result 3
ADC_R4  EQU REGBS+$34   ADC Result 4

* Relative Register Addresses wrt to REGBS

R_PORTE    EQU  $0A    port E
R_CFORC    EQU  $0B    force output compare
R_TCNT     EQU  $0E    timer count
R_TOC5     EQU  $1E    oc5 reg

R_TCTL1    EQU  $20    timer control 1
R_TMSK1    EQU  $22    timer mask 1
R_TFLG1    EQU  $23    timer flag 1

R_TMSK2    EQU  $24    timer mask 2
R_TFLG2    EQU  $25    Timer Flag 2

R_PACTL    EQU  $26     Pulse Accumulator Control Reg

R_BAUD     EQU  $2B    sci baud reg
R_SCCR1    EQU  $2C    sci control1 reg
R_SCCR2    EQU  $2D    sci control2 reg
R_SCSR     EQU  $2E    sci status reg
R_SCDAT    EQU  $2F    sci data reg

R_OPTION  EQU  $39    option reg

R_PORT_A  EQU $00     Port A
R_PORT_B  EQU $04     Port B
R_PORT_C  EQU $03     Port C
R_PORT_D  EQU $08     Port D
R_PORT_E  EQU $0A     Port E

R_PIOC    EQU $02      STAF STAI CWOM HNDS OIN PLS EGA INVB
R_PORTCTL EQU $05
R_DDRC    EQU $07
R_DDRD    EQU $09

R_ADCTL   EQU $30   ADC Control Register
R_ADC_R1  EQU $31   ADC Result 1
R_ADC_R2  EQU $32   ADC Result 2
R_ADC_R3  EQU $33   ADC Result 3
R_ADC_R4  EQU $34   ADC Result 4

* For ADC Channels 0 to 3
ADC_NORM03      EQU $00
ADC_MULT03      EQU $10
ADC_SCAN03      EQU $20
ADC_MULT03SCAN  EQU $30

* For ADC Cahnnels 4 to 7
ADC_NORM47      EQU $04
ADC_MULT47      EQU $14
ADC_SCAN47      EQU $24
ADC_MULT47SCAN  EQU $34

* RTI Clock Rate for PACTL bits RTI0, RTI1 Note DDRA7 is also set $80
* so that Port A bit 7 is an Output
* Given as time periods
RTI_4.10  EQU $80
RTI_8.19  EQU $81
RTI_16.38 EQU $82
RTI_32.77 EQU $83
* Given as Sampling Frequencies
RTI_244Hz EQU $80
RTI_122Hz EQU $81
RTI_61Hz  EQU $82
RTI_31Hz  EQU $83

* Entry points into Buffalo

.WARMST   EQU    $FF7C
.BPCLR    EQU    $FF7F
.RPRINT   EQU    $FF82
.HEXBIN   EQU    $FF85
.BUFFAR   EQU    $FF88
.TERMAR   EQU    $FF8B
.CHGBYT   EQU    $FF8E
.READBU   EQU    $FF91
.INCBUF   EQU    $FF94
.DECBUF   EQU    $FF97
.WSKIP    EQU    $FF9A
.CHKABR   EQU    $FF9D

.UPCASE   EQU    $FFA0
.WCHEK    EQU    $FFA3
.DCHEK    EQU    $FFA6
.INIT     EQU    $FFA9
.INPUT    EQU    $FFAC
.OUTPUT   EQU    $FFAF
.OUTLHL   EQU    $FFB2
.OUTRHL   EQU    $FFB5
.OUTA     EQU    $FFB8
.OUT1BY   EQU    $FFBB
.OUT1BS   EQU    $FFBE
.OUT2BS   EQU    $FFC1
.OUTCRL   EQU    $FFC4
.OUTSTR   EQU    $FFC7
.OUTST0   EQU    $FFCA
.INCHAR   EQU    $FFCD
.VECINT   EQU    $FFD0

* End of Genaral stuff for the ADC Module

ADC_RDY   EQU     $80

* ADC Status bits in ADC_EN
ADC_RUN   EQU     $01

**** Start of Jump Table for ADC Module for Brain Master **********
**** Program Starts here (Table of entry Points and Config values)
     org STREE       * Start at base of EEPROM Block ($B600)
              jmp BUFISIT     * In case PE0 is HIGH start Buffalo anyway

ADC_INIT0:  jmp ADC_INIT    * Cold Start the ADC Module

**** Tbale of Configuration Bytes ******************************
ADC_RATE:   fcb RTI_122Hz    * RTI Rate bits. Other Possible Values are:
* RTI_244Hz RTI_122Hz RTI_61Hz RTI_31Hz

* ADC Channel Enable bits in CHAN_EN
CHAN_1   EQU     $01 * Bit 0 = Chan 1 Enable ( ADC Input PE 0 )
CHAN_2   EQU     $02 * Bit 1 = Chan 2 Enable ( ADC Input PE 1 )
CHAN_3   EQU     $04 * Bit 2 = Chan 3 Enable ( ADC Input PE 2 )
CHAN_4   EQU     $08 * Bit 3 = Chan 4 Enable ( ADC Input PE 3 )
CHAN_5   EQU     $10 * Bit 4 = Chan 5 Enable ( ADC Input PE 4 )
CHAN_6   EQU     $20 * Bit 5 = Chan 6 Enable ( ADC Input PE 5 )
CHAN_7   EQU     $40 * Bit 6 = Chan 7 Enable ( ADC Input PE 6 )
CHAN_8   EQU     $80 * Bit 7 = Chan 8 Enable ( ADC Input PE 7 )

* CHAN_EN0:   fcb CHAN_1+CHAN_2+CHAN_3+CHAN_4
CHAN_EN0:   fcb CHAN_1


* Mode Enable Bits in ADC_MODE
* Enable Code 00 Hex (0000 0000 Binary)
SEND_00    EQU     $01   * Allows code 00 to be sent,
* else code 00 is changed to 01 before sending.

CRLF_ON    EQU     $02   * If set will send CR, LF before Reply Messages

* Sync Protocol 0 Overrides other Sync protocols
SYNC_NONE  EQU     $04   * No Sync Byte (Only useful for one channel

* Sync Protocol 1 ( N Sync, 8-N Digital Input ) if SYNC_* clear
SYNC_ALT   EQU     $08   * Bit 3 Sync Protocol 2, 8 Sync bits, 8 Dig Input Alt
SYNC_BOTH  EQU     $10   * Bit 4 Sync Protocol 3, 8 Sync bits, 8 Dig Input Both

START_ADC  EQU     $20   * Bit 5 Start up with ADC Running, else Startup Paused
SIG_ON     EQU     $40   * Bit 6 Enable Sign On Copyright Message
MSG_ON     EQU     $80   * Bit 7 Enable Messages

NOT_PROT1  EQU     SYNC_ALT+SYNC_BOTH

* ADC_MODE:   fcb MSG_ON+SIG_ON+SYNC_ALT+CRLF_ON
ADC_MODE:   fcb SYNC_NONE+START_ADC


PROT_1_CT:  fcb   3     * Range 2 to 8
* Protocol 1 Shift count for Sync_Count and Digital Input ( i.e. Port C )
* PROT_1_CT is the number of Sync_Count bits.
* The Sync_Count and Port C bits are assembled into D=(A:B)
* Then this value is shifted left by ( 8 - PROT_1_CT ) bits.
* This moves some of Port C bits into A
* and some Sync_Count bits out of A. The result is what is left in A.
* In other words ( 8 - PROT_1_CT ) is the number of Dig Input bits and


IDLE_PULSE: fcb 255 * Range 1 to 255
* Idle Pulse length in units of about 3.53 micro seconds.
* For E Clock = 2MHz. A count of 255 is about 0.9 milli second.


**** Table of Configurable Command Keys ******************************
* These key values may be replaced if desired.
RESUME_KEY: fcb CTLQ  * Resume ADC Character. Pause to Run State
PAUSE_KEY:  fcb CTLV  * Pause ADC Character (Ints still on) Run to Pause State
STOP_KEY:   fcb CTLD  * Stop Character. Disable Interrupts Return to Buffalo


**** Messages Table **************************************************
* These messages may be over written if desired. But must NOT
* be made Longer and must end with EOT.

M_ADC_PAUSE: fcc 'ADC_P'
              fcb EOT

M_ADC_STOP:  fcc 'ADC_S'
              fcb EOT

M_ADC_RUN:   fcc 'ADC_R'
              fcb EOT


**** Cold Start the ADC Module ******************************
ADC_INIT:   ldx #REGBS          * Point to Register Base
             bset R_TMSK2,X $40  * Set Bit RTII

             ldaa R_PACTL,X      * Set RTI Rate
             anda $FC
             ora  ADC_RATE
             staa R_PACTL,X

             ldaa #$7E           * Load Jump Instruction
             staa $00EB          * and save Vection Table

             ldd #ADC_ISR        * Load ADC_ISR Address
             staa $00EC          * and save Hi  byte in Vection Table
             stab $00ED          * and save Low byte in Vection Table

             ldx #REGBS      * Point to Register Base
             ldaa #$00       * Simple i/o on Port C CWOM=0 HNDS=0
             staa R_PIOC,X

             ldaa #$00       * Set Port C Bits 0-7 In
             staa R_DDRC,X

             ldaa ADC_MODE       * Set up Sync Count Mask
             anda #NOT_PROT1
             beq SET_SYNC1
             ldaa #$FF
             bra SET_SYNC2

SET_SYNC1:  ldx #SYNC_MSK_TBL   * Setup Sync Count Mask Value
             jsr GET_P1_SH       * Get Protocol Sync Shift Count and add to X
             ldaa $00,X

SET_SYNC2:  staa SYNC_MSK

             ldy #ADC_MODE
             brclr $00,Y SIG_ON NO_SIG_ON
             ldx #M_SIGON
             bsr MSG_OUT

NO_SIG_ON:  ldx #M_ADC_RUN
             bsr MSG_OUT

             clr SYNC_CT     * clear the ADC Sync Count

             clra
             brclr $00,Y START_ADC GO_PAUSE
             ldaa #ADC_RUN
GO_PAUSE:   staa ADC_EN

             cli             * Enable Intrrupts

**** Poll Input for Command Keys ******************************
ADC_MON:    ldx #ADC_MODE

*            inc PORT_C      * Debug Show we are in polling loop

             jsr .INPUT
             cmpa STOP_KEY
             BEQ ADC_EXIT

             cmpa PAUSE_KEY
             BEQ ADC_PAUSE

             cmpa RESUME_KEY
             BEQ ADC_RESUME

             cmpa #CR_KEY
             BEQ DIG_OUT

**** Still Here, Read as Hex and store in SHFTREG2
             jsr .HEXBIN

*            clr  PORT_C      * Debug Show we are in polling loop

             bra ADC_MON

DIG_OUT:    ldaa SHFTREG2
             staa PORT_B
             bra ADC_MON

ADC_RESUME: ldx #M_ADC_RUN
             bsr MSG_OUT

             clr SYNC_CT     * clear the ADC Sync Count
             ldaa #ADC_RUN   * Re-enable ADC
             staa ADC_EN
             bra ADC_MON

ADC_PAUSE:  clr ADC_EN
             ldx #M_ADC_PAUSE
             bsr MSG_OUT
             bra ADC_MON

ADC_EXIT:   sei                 * Set Interrupt Mask ON
             clr ADC_EN
             ldx #REGBS          * Point to Register Base
             bclr R_TMSK2,X $40  * Clear Bit RTII

             ldx #M_ADC_STOP
             bsr MSG_OUT

             jmp .WARMST     * Return to Buffalo Monitor

**** Output Message only if enabled ************************
* X Must point to message on input
MSG_OUT:    ldy #ADC_MODE
             brclr 0,Y MSG_ON   SKIP_MSG
             brset 0,Y CRLF_ON  CRLF_MSG

             jsr .OUTST0     * No CR LF Before Message
             rts

CRLF_MSG:   jsr .OUTSTR     * Send CR LF before Message
SKIP_MSG:   rts

**** Get Protocol 1 Sync Count Shift Value in B & add to X *********
* B is PROT_1_CT in it on exit
GET_P1_SH:  ldab PROT_1_CT      * Get Shift Count in B
             decb                * Adjust from 1 base to Zero Base
             andb #$07           * Force into range 0 to 7
             abx                 * Add to X
             rts

**** ADC Module Inrerrupt Service Routine *****************
* All Registers saved on Stack by Interrupt h/w in 68HC11
ADC_ISR:    EQU  *
             ldaa #$80
             staa PORT_A     * Show Start of ISR on Port A bit 7

             ldx #ADC_EN     * Check if ADC Scan Enabled
             brset $00,X ADC_RUN ADC_ISR1

             ldab IDLE_PULSE
IDLE:       asla            * do something
             decb
             bne IDLE        * Loop till done
             bra END_ISR

***** Send Sync Byte First  ******************************

ADC_ISR1:   ldx #SYNC_CT        * Point to ADC Sync Count

             ldaa $00,X          * Get Sync Count in A
SYNC_SKP:   inca                * Step on to next Count
             anda SYNC_MSK       * Check if actual bits used are <> 0
             cmpa #$FF           * Also skip Count 255
             beq SYNC_SKP
* as Protocol 2 would need to send a value for 256 (Digital In) but 256 is
* zero in 8 bits and zero is not allowed.
* Protocol 2 needs to send a sync byte for
* every Digital input byte alternating. Since only odd values are used for
* sync count, there nedds to be the same number of even Sync counts
* where Digital Input is sent, hence skip 255 as 0 is also skipped.

             tsta                * Skip Sync Count = 0 for bits used
             bne SYNC_OK
             inca
SYNC_OK:    staa $00,X          * Put back in main memory

             ldx #ADC_MODE
             brset $00,X SYNC_NONE SYNC_P0

             brset $00,X SYNC_ALT  SYNC_P2
             brset $00,X SYNC_BOTH SYNC_P3

* Sync Protocol 1 is:
* PROT_1_CT = Number of bits of Sync_Count (Range 2 to 8)
* ( 8 - PROT_1_CT ) bits of Digital input from Port C
* Sync_Count that ramps up 1 to 2^PROT_1_CT - 1  incrmenting by one
* for each scan of the ADC chans in the ADC_ISR. After max count
* it goes back to 1.

             ldab PORT_C         * Get Input bits from Port C to B
* D=(A:B)=  Sync_Count : Digital_Input (Port_C)
*           b15.....b8 : b7................. b0
             psha                * Save on stack
             pshb

* This is a case statement where a jump is calculated
             ldx  #SHIFT_N       * Get Start of Shift Table in X
             bsr GET_P1_SH       * Get Protocol Sync Shift Count & Add to X

             pulb                * recover D=(A:B)= Sync_Count:Port C
             pula
             jmp 0,X             * Cross Fingers and Jump to Shift line

* Start of Shift line             Shift       PROT_1_CT  No.       No.
*                                 on D          Value    Sync Cnt  Dig Input
*                                 =(A:B)                 Bits      Bits
SHIFT_N:    nop                 *   6             1         2         6
             asld                *   6             2         2         6
             asld                *   5             3         3         5
             asld                *   4             4         4         4

             asld                *   3             5         5         3
             asld                *   2             6         6         2
             asld                *   1             7         7         1
             nop                 *   0             8         8         0

             bra ADC_ISR2

* Sync Protocol 3 is:
* Sync Count sent, all 8 bits every Sweep of ADC Chans
* Range 1 to 254 in tseps of 1 (1,2,3,4,5, .. 253,254)
* Sync count is never 0 or 255
* Digital Inputs sent every Sweep of ADC Chans
SYNC_P3:    bsr BYTE_OUT
             bra SEND_DIG

* Sync Protocol 2 is:
* If Sync Count is odd send Sync Count all 8 bits.
* Range 1 to 253 in steps of 2. (1,3,5,7.. 251,253)
* Note: an Even Sync Count is never sent.
* Sync Count bit 0 is always set when set.
* If Sync Count is even send Digital Input (Port C) all 8 bits.
SYNC_P2:    tab                 * save Sync count in B to test Bit 0
             andb #$01           * Test if Sync Count is ODD
             bne ADC_ISR2        * Send Sync Count
SEND_DIG:   ldaa PORT_C         * Else send Port C all 8 bits

ADC_ISR2:   bsr BYTE_OUT        * Send out the Sync Byte.

**** Start Scanning ADC Channels **************************************
SYNC_P0:    lda  #ADC_MULT03    * Set ADC to SCAN All 4 Channels (0 to 3)
             staa ADCTL          * Start ADC on 4 Channels

             ldaa CHAN_EN0      * Get enable Flags for Chans 0-3 in A
             bsr ADC_LOOP

             lda  #ADC_MULT47    * Set ADC to SCAN All 4 Channels (4 to 7)
             staa ADCTL

             ldaa CHAN_EN0      * Get enable Flags for Chans 4-7
             lsra               * Shift to bits 0-3 in A
             lsra
             lsra
             lsra
             bsr ADC_LOOP

END_ISR:    ldx #REGBS        * Signal End of ISR to Real Time Clock
             bclr R_TFLG2,X $3F

             clr PORT_A      * Show End of ISR on Port A bit 7

             rti             * End of ISR

**********************************************************************
* Sends byte in Reg A to SCI
BYTE_OUT:   pshb

*            ldab #$02       * Debug
*            stab PORT_C     * Debug

             ldab ADC_MODE   * Check if allowed to send $00
             andb #SEND_00
             bne  B_OUT2
             tsta
             bne  B_OUT2
             inca

B_OUT2:     ldab SCSR       * Read sci status reg
             bitb #$80       * loop until tdre=1
             beq  B_OUT2
             nop             * mimic timing of Buffalo Output routine
             staa SCDAT      * Send Byte out

*            clr PORT_C      * Debug

             pulb
             rts

**********************************************************************
* Loop through 4 ADC Channels and test if each is enabled
* Skip those that are not.
* A, B, X all modified
* A must be setup with Flag bits in low for positions (0-3)
* for each of the channels to be sent out

ADC_LOOP:   EQU  *
*             ldab #$04       * Debug
*             stab PORT_C     * Debug

             staa CHAN_EN
             ldx #ADCTL
             ldab #$01       * Mask that is scanned through all channels

ADC_WAIT:   brclr $00,X ADC_RDY ADC_WAIT

             inx                 * Point X to ADC Results Registers

NEXT_ADC:   EQU  *
*            ldaa #$04       * Debug
*            staa PORT_C     * Debug

             tba                 * Get Chan Select Mask
             anda CHAN_EN        * Test against Chan Enable Mask
             beq SKIP_CHAN
             ldaa $00,X          * Get ADC value for Enabled chan
             bsr BYTE_OUT        * and Send it out

SKIP_CHAN:  EQU  *
*            clr PORT_C          * Debug

             inx                 * Point to next channel
             aslb                * Shit Select mask to next channel
             cmpb #$10           * Test Mask if end of loop
             blt NEXT_ADC
             rts


**** Short Form Copy Right Message ******************************
M_SIGON:     fcc 'BM_CR_WRSW&TFC'


              fcb EOT

**** Table of Masks for Sync Count when < 8  bits used in count
SYNC_MSK_TBL: fcb  $03          * Shift 6   PROT_1_CT = 1  Sync 2 Dig In 6
               fcb  $03          * Shift 6   PROT_1_CT = 2  Sync 2 Dig In 6
               fcb  $07          * Shift 5   PROT_1_CT = 3  Sync 3 Dig In 5
               fcb  $0F          * Shift 4   PROT_1_CT = 4  Sync 4 Dig In 4

               fcb  $1F          * Shift 3   PROT_1_CT = 5  Sync 5 Dig In 3
               fcb  $3F          * Shift 2   PROT_1_CT = 6  Sync 6 Dig In 2
               fcb  $7F          * Shift 1   PROT_1_CT = 7  Sync 7 Dig In 1
               fcb  $FF          * Shift 0   PROT_1_CT = 8  Sync 8 Dig In 0

**** RAM Table *******************************************************
             org $0100
SYNC_CT:    rmb 1           * ADC Sync Count Range 1 to 254
ADC_EN:     rmb 1           * ADC Enable Flags Set Bit 0 = Run
CHAN_EN:    rmb 1           * ADC Channel Enables Bits 0-3 Only used

SYNC_MSK:   rmb 1           * Mask to check Sync Count when < 8 bits used

**** end of File BM_11.ASM ****************************************

#################################################

ADC Module Ver 0.91 for Brain Master

Written by and (c) W. Robert S. Webber Ph.D. CEng. MIEE
Squarey Basement Software

Date Wed  5 Jul 1995   BM_10.ASM   Ver 0.90
Revised 6 Sept 1995    BM_11.ASM   Ver 0.91

Copyright ========================================================
As with any freeware I would make no guarantee, warranty implied or
otherwise that the code is good for anything, will not harm anyone
however used. That is, what ever happens or does not happen as a
result of using or not using this code is not my fault or
responsibility.

This program is licensed to Tom Collura and the Brain Master
project to be freely distributed as part of that project.

Any derived work would be the property and responsibility of the
person deriving such work. An acknowledgement of the original
source would be appreciated.
=================================================================

Changes:
New Equates added for Setting Sampling frequency

> * Given as Sampling Frequencies
> RTI_244Hz EQU $80
> RTI_122Hz EQU $81
> RTI_61Hz  EQU $82
> RTI_31Hz  EQU $83


Replace line 228 in c:\ap2\68hc11\brain_m\BM_10.ASM
< ADC_RATE:   fcb RTI_8.19    * RTI Rate bits.

with lines 234-235 from c:\ap2\68hc11\brain_m\BM_11.ASM
> ADC_RATE:   fcb RTI_122Hz    * RTI Rate bits. Other Possible
Values are:
> * RTI_244Hz RTI_122Hz RTI_61Hz RTI_31Hz


Replace line 248 in c:\ap2\68hc11\brain_m\BM_10.ASM
< CRLF_ON    EQU     $04   * If set will send CR, LF before Reply
Messages

with lines 255-258 from c:\ap2\68hc11\brain_m\BM_11.ASM
> CRLF_ON    EQU     $02   * If set will send CR, LF before Reply
Messages
>
> * Sync Protocol 0 Overrides other Sync protocols
> SYNC_NONE  EQU     $04   * No Sync Byte (Only useful for one
channel

After line 459 in c:\ap2\68hc11\brain_m\BM_10.ASM insert lines
470-471 from c:\ap2\68hc11\brain_m\BM_11.ASM
>             brset $00,X SYNC_NONE SYNC_P0
>


Replace line 521 in c:\ap2\68hc11\brain_m\BM_10.ASM
<             lda  #ADC_MULT03    * Set ADC to SCAN All 4 Channels
(0 to 3)

with line 533 from c:\ap2\68hc11\brain_m\BM_11.ASM
> SYNC_P0:    lda  #ADC_MULT03    * Set ADC to SCAN All 4 Channels
(0 to 3)


(0)  The ADC module is a general purpose program for the 68HC11
that allows for analog data to be collected from the analog Port E
and sent back via the serial port. In addition, digital data, as a
continuous stream, can be read from Port C and sent back with the
analog data. Digital data may be sent to the ADC Module and appears
as output on Port B.
      In order to maintain sync with the ADC module, one or two sync
bytes are sent at the start of ever channel scan. There are three
protocols for the sync byte, depending on how much digital input
data is needed and how often it is required.

(1.0) Sync Protocol 0 Is a simple mode for use with one ADC
channel.  If this protocol is selected then no Sync byte is sent.
The Control task is still active so that the ADC Module can be
paused, resumed and control can be returned to the Buffalo monitor
(Added with BM_11.ASM Ver 0.91)

(1.1) Sync Protocol 1 One byte, sync and digital combined
      The sync byte is made up of two bit fields. The high field is
the sync count itself, while the low field is the upper part of
Port C, the digital input port. This protocol is enabled by
clearing both bits SYNC_ALT ($08) and SYNC_BOTH ($10) in ADC_MODE
(B608). The width of the sync count and hence the number of digital
input bits can be varied by setting a value in PROT_1_CT (B609).
The range of this value is 2 to 8 meaning the number of bits of
sync count as follows:

PROT_1_CT  No.       No.
Value    Sync Cnt  Dig Input
(B609)   Bits      Bits   Port C bits read & position in sync byte
                           S = sync bit, D = Digital Input bit
   2         2         6   SSDD DDDD
                             76 5432 Position of Port C bits

   3         3         5   SSSD DDDD
                              7 6543

   4         4         4   SSSS DDDD
                                7654

   5         5         3   SSSS SDDD
                                 765

   6         6         2   SSSS SSDD
                                  76
   7         7         1   SSSS SSSD
                                   7

   8         8         0   SSSS SSSS


(2) Sync Protocol 2 One byte, sync and one byte digital inputs
alternating. For this protocol the digital input is only sampled
every other scan of the ADC channels. How ever the sync burned is
still only one extra byte in the data stream Details are given in
Sync Protocol 3.

(3) Sync Protocol 3 Two bytes, sync followed by digital input.
      These two protocols are very similar and are not described
separately. The only difference is that in Protocol 2 the sync byte
is sent on the first scan of the adc channels then alternates
between sending the digital input port byte with the sync byte.
Since this protocol alternates only odd values of sync are sent,
i.e 01, 03, 05, etc .... Where the even sync count would have been,
the digital input is sent. For protocol 3 both sync and digital
input are sent for each sweep of the analog channels. For both
protocols the sync count starts a 01 and goes up to 253 for
protocol 2 and 254 for protocol 3. Sync count 255 is never used.


(4) ADC Commands
      There are 3 single byte commands and two multi byte commands
for the ADC module.

Start ADC Module = G B603 Cr
This starts the ADC Module program. Once started the ADC Module
polls for commands while sending ADC & digital data back over the
serial line.

RUN (or RESUME) = Ctrl Q
This command Starts the ADC Module sending data over the serial
line.

STOP = Ctrl D
This command completely shuts down the ADC Module and returns
controls to Buffalo

PAUSE = Ctrl Q
This command Pauses the ADC Module. Interrupts are still enabled,
but no serial data is sent. The ADC Module still polls for
commands, so that digital outputs can be sent to port B.

Send ASCII Hex to digital output Port B = HH Cr
HH is the ASCII Hex value ( 00 to FF ) to be sent to Port B




(5) Ports used on 68HC11

Port A bit 7 ADC ISR Activity bit. This is high While the ISR is
active. It is set to 1 at the start of the ISR and set to 0 at the
end.

Port B all bits used as digital output.

Port C all or some bits used as digital input

Port E Analog input. All 8 channels can be used.



(6) Example session showing control passed to and from ADC Module
program:

      Interactive session with ADC Module code showing Start up and
transfer of control to the ADC module and returning control back to
Buffalo Monitor.

      The example is from an actual session where ASCII down load
was started before cold boot and remained in effect for the whole
session. All responses from the 68HC11 are shown as Hex with ASCII
shown following ':'.  Above each reply is a brief description of
the action that caused the reply.

Start of Session
Responce From ADC Module Cold Boot Sign On Message.
Reply:
0D 0A 42 55  46 46 41 4C  4F 20 33 2E  32 20 28 69
6E 74 29 20  2D 20 42 69  74 20 55 73  65 72 20 46
61 73 74 20  46 72 69 65  6E 64 6C 79  20 41 69 64
20 74 6F 20  4C 6F 67 69  63 61 6C 20  4F 70 65 72
61 74 69 6F  6E :
BUFFALO 3.2 (int) - Bit User Fast Friendly Aid to Logical Operation

Send CR to Complete Start UP and Display Prompt.
Reply:
0D 0A 3E : >

Send Ctrl V to get State of System
Reply:
16 0D 0A               : echo Ctrl V
0D 0A 57 68 61 74 3F   : What?
0D 0A 3E               : >

Send Ctrl D to get State of System
Reply:
04 0D 0A               : echo Ctrl D
0D 0A 57 68  61 74 3F  : What?
0D 0A 3E               : >

Start ADC Module by sending g b603
Reply:
67 20  62 36 30 33     : g b603
0D 0A
0D 0A  42 4D 5F 43 52 5F 57 52  53 57 26 54  46 43  :
BM_CR_WRSW&TFC
0D 0A  41 44 43 5F 52  : ADC_R

ADC Module starts up in Pause Mode (Interrupts active but no data
sent)
ADC_R is always sent for both Startup in pause and running modes.

Send Pause Command
Reply:
0D 0A 41  44 43 5F 50   : ADC_P

Send Run Commands
Reply:
0D 0A 41 44  43 5F 52   : ADC_R

Data starts coming, Sync Byte followed by 3 channels of Analog data
Sync Count is highest 3 bits of Sync Bytes.
Lower 5 bits are Digital Input lines form Port C, Bits b7 to b3

20 50 50 50
40 50 50 50
60 50 50 50
etc ...
40  50 50 50
60  50 50 50
80  50 50 50

Pause Command Ctrl V Sent
Reply:
0D  0A 41 44 43  5F 50  : ADC_P

Stop Command Ctrl D Sent
Reply:
0D 0A  41 44 43 5F 53   : ADC_S
0D 0A 3E                : >
Now back in Buffalo Monitor

Restart ADC Module by sending g b603
Reply:
67 20 62 36  30 33      : g b603

0D 0A
0D 0A 42 4D 5F 43 52 5F  57 52 53 57  26 54 46 43 : BM_CR_WRSW&TFC
0D 0A 41 44 43 5F 52  : ADC_R

Send stop Ctrl D Command
Reply:
0D 0A 41 44 43 5F 53  : ADC_S
0D 0A 3E              : >

Now back in Buffalo Monitor

Send stop Ctrl D Command again
Reply:
04 0D 0A              : echo Ctrl D
0D 0A 57 68  61 74 3F : What?
0D 0A 3E              : >

Press reset Button i.e. cold start
Reply:
0D 0A 42 55 46 46
41 4C 4F 20  33 2E 32 20  28 69 6E 74  29 20 2D 20
42 69 74 20  55 73 65 72  20 46 61 73  74 20 46 72
69 65 6E 64  6C 79 20 41  69 64 20 74  6F 20 4C 6F
67 69 63 61  6C 20 4F 70  65 72 61 74  69 6F 6E :
BUFFALO 3.2 (int) - Bit User Fast Friendly Aid to Logical Operation

Send CR to Complete Start UP and Display Prompt:
Reply:
0D 0A 3E              : >


Send stop Ctrl D Command
Reply:
04 0D 0A              : echo Ctrl D
0D 0A 57 68 61 74 3F  : What?
0D 0A 3E              : >

End of session



(7) ADC States.
The ADC Module can be in any of 5 states. Three of these are for
the monitor and 2 are for the ADC Porgram itself. The monitor
states are M0 to M2 and the ADC states are A0 and A1. A description
of each state and how to test for it is given.

M0 No power. Send Ctrl V and get no responce in 10 msec, send CR
get no responce in 10 msec.

M1 Initial power up state. (before Buffalo has received any serial
data). On entry to this state, Buffalo sends its sign on messgae.
To test for this state, send Ctrl V, no response in 10 msec, send
CR, get responce:
0D 0A 3E  : >

M2 Buffalo fully initilised. In this state a single CR will repeat
the last command. This is unpredictable and may well start the ADC
module if last command was G B603. To test for this state, send
Ctrl V which will be echoed back. At this point send CR to complete
the command. The ADC Module will respond with:
04                    : Ctrl V
0D 0A 57 68 61 74 3F  : What?
0D 0A 3E              : >

A0 ADC Module program is active but paused. Interrupts are on, Port
A bit 7 is pulsing, but no serial data is being sent.
This state is tested by sending Ctrl V, to which ADC Module
responds
0D  0A 41 44 43  5F 50  : ADC_P

A1 ADC Module program is active and serial data is being sent. This
state can be detected by receiving an endless stream of characters.
On the other hand one can send Ctrl V which will force it to state
A0 and respond with ADC_P. If on the other hand Buffalo is running,
the unit will respond by echoing Ctrl V.

(8) State transitions:
M0 -> M1 Apply power
M1 -> M2 send CR
M2 -> A0 send g b603 and have bit 5, $20 clear in ADC_MODE (B608)
M2 -> A1 send g b603 and have bit 5, $20 set   in ADC_MODE (B608)
A1 -> A0 send Ctrl V
A0 -> A1 send Ctrl Q
A0,A1 - > M2 send Ctrl D
A0,A1,M1,M2 -> M0 pull power.


(9) ADC Modes, Configuration Options and code address:
The 4 character hex value begining with "B..." at the start of each
line is the location of the variable in EEPROM that may be
modified. These addresses should not change as changes are made to
the code

B606 ADC_RATE:   fcb RTI_8.19    * RTI Rate bits (see .LST file).
RTI_4.10  EQU $80   256 Samples/Sec
RTI_8.19  EQU $81   128 Sample/Sec
RTI_16.38 EQU $82   64  Samples/Sec
RTI_32.77 EQU $83   32  Samples/Sec


B607 CHAN_EN0:   fcb CHAN_1+CHAN_2+CHAN_3+CHAN_4
      Any Combination of channels may be enabled
0001 CHAN_1  EQU $01 * Bit 0 = Chan 1 Enable ( ADC Input PE 0 )
0002 CHAN_2  EQU $02 * Bit 1 = Chan 2 Enable ( ADC Input PE 1 )
0004 CHAN_3  EQU $04 * Bit 2 = Chan 3 Enable ( ADC Input PE 2 )
0008 CHAN_4  EQU $08 * Bit 3 = Chan 4 Enable ( ADC Input PE 3 )
0010 CHAN_5  EQU $10 * Bit 4 = Chan 5 Enable ( ADC Input PE 4 )
0020 CHAN_6  EQU $20 * Bit 5 = Chan 6 Enable ( ADC Input PE 5 )
0040 CHAN_7  EQU $40 * Bit 6 = Chan 7 Enable ( ADC Input PE 6 )
0080 CHAN_8  EQU $80 * Bit 7 = Chan 8 Enable ( ADC Input PE 7 )


Mode Enable Bits in ADC_MODE
B608 ADC_MODE: fcb MSG_ON+SIG_ON+SYNC_ALT+CRLF_ON

SEND_00 EQU $01   * Allows code 00 to be sent, else code 00 is
                       changed to 01 before sending.

CRLF_ON EQU $02   * If set will send CR, LF before
                     Reply Messages
                     (Note: This bit was $04 in BM_10 Ver 0.90)

SYNC_NONE EQU $04  * Bit 2 Sync Protocol 0,
                     No Sync Byte sent. Only useful for one channel
                     ( Added with BM_11 Ver 0.91)


Sync Protocol 1 ( N Sync, 8-N Digital Input ) if SYNC_* clear
i.e. Bit 3 and Bit 4


SYNC_ALT EQU $08  * Bit 3 Sync Protocol 2,
                     8 Sync bits, 8 Dig Input Alternating

SYNC_BOTH EQU $10 * Bit 4 Sync Protocol 3,
                     8 Sync bits, 8 Dig Input Both


START_ADC EQU $20 * Bit 5 Start up with ADC Running,
                           else Startup Paused.

SIG_ON    EQU $40 * Bit 6 Enable Sign On Copyright Message
                          Bit 7 must also be on for Sign On to
                          to appear.

MSG_ON    EQU $80 * Bit 7 Enable all reply messages


B609 PROT_1_CT: fcb 3  * Range 2 to 8
Protocol 1 Shift count for Sync_Count and Digital Input ( i.e. Port
C ) PROT_1_CT is the number of Sync_Count bits.
The Sync_Count and Port C bits are assembled into D=(A:B), then
this value is shifted left by ( 8 - PROT_1_CT ) bits.
this moves some of Port C bits into A and some Sync_Count bits out
of A. The result is what is left in A. In other words ( 8 -
PROT_1_CT ) is the number of Dig Input bits.



B60A IDLE_PULSE: fcb 255 * Range 1 to 255
Idle Pulse length in units of about 3.53 micro seconds.
For E Clock  2MHz. A count of 255 is about 0.9 milli second.
The pulse appears on Port A bit 7 when the Interrupt service
routine (ISR) in active. When ADC Module is paused its length is
goverened by this value. When the ADC Module is sending data, the
pulse lenght is goverened by the amount of data to be sent for
every sweep of the channels. The more the data, the longer the
pulse.



(10) Table of Configurable Command Keys
These key values may be replaced if desired.

B60B RESUME_KEY: fcb CTLQ  * Run or Resume ADC Character.
Pause to Run State

B60C PAUSE_KEY:  fcb CTLV  * Pause ADC Character (Ints still on)
Run to Pause State

B60D STOP_KEY:   fcb CTLD  * Stop Character. Disable Interrupts and
Return to Buffalo



(11) Messages Table. These messages may be over written if desired.
But must NOT be made Longer and must end with EOT ($04).
B60E M_ADC_PAUSE: fcc 'ADC_P'
b613 fcb EOT

B614 M_ADC_STOP:  fcc 'ADC_S'
B619 fcb EOT

B61A M_ADC_RUN:   fcc 'ADC_R'
B61F fcb EOT




(12) Example Dumps of the ADC Module running. Each dump starts from
when the ADC Module enters Run State A0 -> A1 i.e. it receives
Ctrl Q:

Configuration is:
Reply Responce Enabled
3 ADC channels
Protocol 1, 5 Sync bits & 3 digital input bits (b7 to b5)
      from Port C in positions b2 to b0.
      Digital inputs are all 1s.
      Sync sent first ADC Channels
0D 0A 41 44  43 5F 52 0F  50 50 50 17  50 50 50 1F
50 50 50 27  50 50 50 2F  50 50 50 37  50 50 50 3F
50 50 50 47  50 50 50 4F  50 50 50 57  50 50 50 5F
50 50 50 67  50 50 50 6F  50 50 50 77  50 50 50 7F
50 50 50 87  50 50 50 8F  50 50 50 97  50 50 50 9F
50 50 50 A7  50 50 50 AF  50 50 50 B7  50 50 50 BF
50 50 50 C7  50 50 50 CF  50 50 50 D7  50 50 50 DF
50 50 50 E7  50 50 50 EF  50 50 50 F7  50 50 50 FF Sync rolls over
50 50 50 0F  50 50 50 17  50 50 50 1F  50 50 50 27
50 50 50 2F  50 50 50 37  50 50 50 3F  50 50 50 47
50 50 50 4F  50 50 50 57  50 50 50 5F  50 50 50 67
50 50 50 6F  50 50 50 77  50 50 50 7F  50 50 50 87


Configuration is:
Reply Responce Enabled
3 ADC channels
Protocol 1, 4 Sync bits & 4 digital input bits (b7 to b4)
      from Port C in positions b3 to b0.
      Digital inputs are all 1s.
      Sync sent first ADC Channels
0D 0A 41 44  43 5F 52 1F  50 50 50 2F  50 50 50 3F
50 50 50 4F  50 50 50 5F  50 50 50 6F  50 50 50 7F
50 50 50 8F  50 50 50 9F  50 50 50 AF  50 50 50 BF
50 50 50 CF  50 50 50 DF  50 50 50 EF  50 50 50 FF Sync rolls over
50 50 50 1F  50 50 50 2F  50 50 50 3F  50 50 50 4F
50 50 50 5F  50 50 50 6F  50 50 50 7F  50 50 50 8F
50 50 50 9F  50 50 50 AF  50 50 50 BF  50 50 50 CF
50 50 50 DF  50 50 50 EF  50 50 50 FF  50 50 50 1F Sync rolls over
50 50 50 2F  50 50 50 3F  50 50 50 4F  50 50 50 5F
50 50 50 6F  50 50 50 7F  50 50 50 8F  50 50 50 9F
50 50 50 AF  50 50 50 BF  50 50 50 CF  50 50 50 DF


Configuration is:
Reply Responce Enabled
3 ADC channels
Protocol 2, 8 Sync bits & 8 digital input bits (b7 to b0) Port C
      Alternating. Sync sent first then digital input = all 1s.
0D 0A 41 44  43 5F 52 01  50 50 50 FF  50 50 50 03
50 50 50 FF  50 50 50 05  50 50 50 FF  50 50 50 07
50 50 50 FF  50 50 50 09  50 50 50 FF  50 50 50 0B
50 50 50 FF  50 50 50 11  50 50 50 FF  50 50 50 13
50 50 50 FF  50 50 50 15  50 50 50 FF  50 50 50 17
50 50 50 FF  50 50 50 19  50 50 50 FF  50 50 50 1B
50 50 50 FF  50 50 50 1D  50 50 50 FF  50 50 50 1F
etc ...
50 50 50 FF  50 50 50 F1  50 50 50 FF  50 50 50 F3
50 50 50 FF  50 50 50 F5  50 50 50 FF  50 50 50 F7
50 50 50 FF  50 50 50 F9  50 50 50 FF  50 50 50 FB
50 50 50 FF  50 50 50 FD  50 50 50 FF  50 50 50 01  Sync rolls over
50 50 50 FF  50 50 50 03  50 50 50 FF  50 50 50 05
50 50 50 FF  50 50 50 07  50 50 50 FF  50 50 50 09
50 50 50 FF  50 50 50 0B  50 50 50 FF  50 50 50 0D



Configuration is:
Reply Responce Enabled
3 ADC channels
Protocol 2, 8 Sync bits & 8 digital input bits (b7 to b0) Port C
      Alternating. Sync sent first then digital input = all 0s.
      Note: Although all Digital inputs are 0, the transmitted value
      has been incremented by 1 o avoid a value of 00. This feature
      can be disabled, i.e. allowing 00 to be transmitted by setting
      bit b0 in ADC_MODE (B608).
0D 0A 41 44  43 5F 52 01  50 50 50 01  50 50 50 03
50 50 50 01  50 50 50 05  50 50 4E 01  50 50 50 07
50 50 50 01  50 50 50 09  50 50 50 01  50 50 50 0B
50 50 50 01  50 50 50 0D  50 50 50 01  50 50 50 0F
50 50 50 01  50 50 50 11  50 50 50 01  50 50 50 13
50 50 50 01  50 50 50 15  4F 50 50 01  50 50 50 17
50 50 50 01  50 50 50 19  50 50 50 01  50 50 50 1B
50 50 50 01  50 50 50 1D  50 50 50 01  50 50 50 1F
50 50 50 01  50 50 50 21  50 50 50 01  50 50 50 23

Configuration is:
Reply Responce Enabled
2 ADC channels
Protocol 3, 8 Sync bits & 8 digital input bits (b7 to b3) Port C
      Both Sync sent first then digital input = all 1s.
0D 0A 41 44  43 5F 52 01  FF 50 50 02  FF 50 50 03
FF 50 50 04  FF 50 50 05  FF 50 50 06  FF 50 50 07
FF 50 50 08  FF 50 50 09  FF 50 50 0A  FF 50 50 0B
FF 50 50 0C  FF 50 50 0D  FF 50 50 0E  FF 50 50 0F
FF 50 50 10  FF 50 50 11  FF 50 50 12  FF 50 50 13
FF 50 50 14  FF 50 50 15  FF 50 50 16  FF 50 50 17
FF 50 50 18  FF 50 50 19  FF 50 50 1A  FF 50 50 1B
etc ...
FF 50 50 F2  FF 50 50 F3  FF 50 50 F4  FF 50 50 F5
FF 50 50 F6  FF 50 50 F7  FF 50 50 F8  FF 50 50 F9
FF 50 50 FA  FF 50 50 FB  FF 50 50 FC  FF 50 50 FD
FF 50 50 FE  FF 50 50 01  FF 50 50 02  FF 50 50 03 Sync Roll over
FF 50 50 04  FF 50 50 05  FF 50 50 06  FF 50 50 07
FF 50 50 08  FF 50 50 09  FF 50 50 0A  FF 50 50 0B
FF 50 50 0C  FF 50 50 0D  FF 50 50 0E  FF 50 50 0F
tfcdev 15:

hi
i'm seeing much action from many people wanting to build an eeg . maybe we can
collaborate .
i'm trying to think of ways we can do that .
first of course we have to decide on what to work .
i see many people want to do many things.
one idea that might be good is :
maybe we should collaborate on a real low cost eeg machine ?
because joerg / morrirz are doint modulareeg which supposed to be good eeg .high
quality .
of course we have common specs to define , and what excatly will the machine be
but still is this goal suits you people ?
anyone who likes to help , please raise his hands :)

also we need to find a way to work share across the net to do this
mosteffectivly , i
think .

sincerly yaniv vilnai

Hi Andreas,

----- Original Message -----
From: sleeper75se <sleeper75se@...>
To: <buildcheapeeg@yahoogroups.com>
Sent: Wednesday, January 02, 2002 10:09 PM
Subject: [buildcheapeeg] Re: Input protection


> Hi Joerg,
>
> --- In buildcheapeeg@y..., "Joerg Hansmann" <info@j...> wrote:
> > Lowest possible operating voltage of the used OPs.
> > Are they all rail-to rail ? (Or at least near to that)
>
> Ah, now I understand. Ok, the datasheet for LT1012 says this:
>
> Minimum supply voltage: +/-1.2 volts
> CM-range: typically V+ - 0.9V and V- + 0.9V
> So powering it at +/- 2.5V would give you a common mode range of +/-
> 1.6V.

That should be OK.
I have done a few experiments with my comEEG and have got about 50mVp-p
50Hz common mode voltage 1m away from power lines and
350mVp-p with one foot stepping on an (isolated) 3-wire 230V
power line. (all without DRL)

> CMRR is 40dB at 1MHz, falling about 20dB per decade, by the way.
> It is not rail-to-rail, at +/-15V supply voltage the swing is
> characterized to typically +/- 14V. I don't know how that scales, but
> a wild guess is +/- 1.5V at 2.5V supply voltage.

Should be OK if offset voltages are cancelled / or gain
of each stage is not too high.

> > Only in differential mode as far as I can see.
> > However common mode rejection of OPs decreases at high
> > frequencies. So HF should also be shunted for common mode.
>
> Yes, you are right, it does not attenuate the HF common mode signals,
> but one could argue that those are not amplified either...

But the HF gets demodulated at non-linear components in the OP and
thereby adds a seemingly unpredictable offset voltage that
really is music from the next AM-transmitter.

> Of course, better safe than sorry, but isn't it hard to get the the
> ground/shield quiet enough for what is essentially a HF short-circuit
> to the most sensitive, high-impedance part of the system?

The ground plane should have really low-impedance. Alternatively
or additionally the Cs could be connected very close to the
electrode connector and a metal casing could be used (at least
for the input stage because it could corrupt isolation if it
extends over the optocoupler stage).

> Hmm, I think we have reached the point where we need to build and
> test.

Experiments are always good...

> > Oops, I did not realize that shottky diodes were so bad.
> > Are BAT48 diodes(max 40V, 0.35 A) comparable with BAR42
> > (max 30V,0.1 A)?
> > I fear they are even worse ...
>
> Unfortunately I was unable to find a model for BAT48 and the data
> sheet only characterized the reverse leakage at 10V and up... (2uA)

I have simulated a BAT 54 (30V, 0.3A) with switchercad
and can`t believe how bad the leak current/impedance is compared with
a npn (e.g 2n3391)


> > > active emergency-shutoff...
> >
> > I have had the same idea, but could not find a
> > way to measure the error-condition without
> > producing noise, degrading impedance or adding new
> > risk by the protection circuit.
>
> A differential amplifier built from two N-channel MOSFETS measuring
> the voltage drop across a resistor, would that work? They are nice
> and quiet AFAIK.

And have ESD sensitve gates or ... protection diodes at their gates.

> Since the amplifier would be discrete, we could
> limit the drain-source current using large resistors (100K+) and keep
> the user safe.

Why not construct the 1st amplifier stage with discrete components
to get hi-impedance and low noise ?
(However do not know enough about analog design to do that...)

> Noise would not be that important if the system
> averages the measurement over perhaps 100ms.

I thought more of the additional noise from the protection circuit that could
affect the EEG-measurement...

> A high overcurrent

Through the test subject ?

> would
> trigger the shut-off circuitry faster than an overcurrent that is
> only a little bit over the limit.

I have no idea, what IEC601-1 says how long the
current limits may be exceeded.


Regards,

Joerg

Hi Joerg,

--- In buildcheapeeg@y..., "Joerg Hansmann"
<info@j...> wrote:

> But the HF gets demodulated at non-linear components
in the OP and
> thereby adds a seemingly unpredictable offset
voltage that
> really is music from the next AM-transmitter.

Ah! Then we can listen to music while we're measuring
EEG! :-)
Seriously though, I see your point...

> I have simulated a BAT 54 (30V, 0.3A) with
switchercad
> and can`t believe how bad the leak current/impedance
is compared with
> a npn (e.g 2n3391)

It seems we are limited to transistors then, but maybe
we don't need anything else. (Read on...)

> > > > active emergency-shutoff...

Is a certified PITA.

I've done some experiments (aka simulations) with a
FET-based current detector. Building a differential
amplifier is simple enough, but the gate-current for
the types of NMOS transistors I tried, got rather high
(1nA).

In other words: It would certainly measure
overcurrents but destroy the EEG signal at the same
time.

I went to Biosemi (where else?) and read about their
protection method once more:

http://www.biosemi.com/faq/limit_current.htm

If I understand it correctly, they only check for
short-circuits during power-up. If that's good enough
for them, why should it not be good enough for us?
Single faults are handled by the DRL, and double
faults are "very unlikely".

Here's an outline of a crude method for the
fault-checking:

We connect the amplifier input to the electrode
through a relay. The input can be switched to either
the electrode or a 1Mohm resistor connected to ground.
A window comparator measures the voltage over the
resistor and signals an error if it detects more than
+/- 5mV. The 5mV => 5uA through a 1K resistor.

When the EEG is turned on, it does a self test -
checking all amplifiers for errors before connecting
the patient.

I don't know what kind of errors relays introduce
(thermocouple voltage offsets?), but there are types
designed for low-level signals such as audio, that
cost about €3-€6 each (we would need at least four).

So, what do you think?

Regards,

Andreas

_____________________________________________________
Do You Yahoo!?
se.yahoo.com

Hi,

here is a new protection circuit that limits user current
to about 5uA if a worst case input stage failure occurs
(inputs internally shorted to supply rails).
The serial impedance of the circuit is only 6 kOhms.
The parallel DC resistance is a few 100 GigaOhms (The y-axis
says GA, but it is really U/I and should be GOhms).


Regards,

  Joerg

----- Original Message -----

From: Joerg Hansmann

To: buildcheapeeg@yahoogroups.com

Sent: Friday, January 04, 2002 3:46 PM

Subject: Re: [buildcheapeeg] Re: Input protection

Hi Andreas,

----- Original Message -----
From: sleeper75se <sleeper75se@...>
To: <buildcheapeeg@yahoogroups.com>
Sent: Wednesday, January 02, 2002 10:09 PM
Subject: [buildcheapeeg] Re: Input protection


> Hi Joerg,
>
> --- In buildcheapeeg@y..., "Joerg Hansmann" <info@j...> wrote:
> > Lowest possible operating voltage of the used OPs.
> > Are they all rail-to rail ? (Or at least near to that)
>
> Ah, now I understand. Ok, the datasheet for LT1012 says this:
>
> Minimum supply voltage: +/-1.2 volts
> CM-range: typically V+ - 0.9V and V- + 0.9V
> So powering it at +/- 2.5V would give you a common mode range of +/-
> 1.6V.

That should be OK.
I have done a few experiments with my comEEG and have got about 50mVp-p
50Hz common mode voltage 1m away from power lines and
350mVp-p with one foot stepping on an (isolated) 3-wire 230V
power line. (all without DRL)

> CMRR is 40dB at 1MHz, falling about 20dB per decade, by the way.
> It is not rail-to-rail, at +/-15V supply voltage the swing is
> characterized to typically +/- 14V. I don't know how that scales, but
> a wild guess is +/- 1.5V at 2.5V supply voltage.

Should be OK if offset voltages are cancelled / or gain
of each stage is not too high.

> > Only in differential mode as far as I can see.
> > However common mode rejection of OPs decreases at high
> > frequencies. So HF should also be shunted for common mode.
>
> Yes, you are right, it does not attenuate the HF common mode signals,
> but one could argue that those are not amplified either...

But the HF gets demodulated at non-linear components in the OP and
thereby adds a seemingly unpredictable offset voltage that
really is music from the next AM-transmitter.

> Of course, better safe than sorry, but isn't it hard to get the the
> ground/shield quiet enough for what is essentially a HF short-circuit
> to the most sensitive, high-impedance part of the system?

The ground plane should have really low-impedance. Alternatively
or additionally the Cs could be connected very close to the
electrode connector and a metal casing could be used (at least
for the input stage because it could corrupt isolation if it
extends over the optocoupler stage).

> Hmm, I think we have reached the point where we need to build and
> test.

Experiments are always good...

> > Oops, I did not realize that shottky diodes were so bad.
> > Are BAT48 diodes(max 40V, 0.35 A) comparable with BAR42
> > (max 30V,0.1 A)?
> > I fear they are even worse ...
>
> Unfortunately I was unable to find a model for BAT48 and the data
> sheet only characterized the reverse leakage at 10V and up... (2uA)

I have simulated a BAT 54 (30V, 0.3A) with switchercad
and can`t believe how bad the leak current/impedance is compared with
a npn (e.g 2n3391)


> > > active emergency-shutoff...
> >
> > I have had the same idea, but could not find a
> > way to measure the error-condition without
> > producing noise, degrading impedance or adding new
> > risk by the protection circuit.
>
> A differential amplifier built from two N-channel MOSFETS measuring
> the voltage drop across a resistor, would that work? They are nice
> and quiet AFAIK.

And have ESD sensitve gates or ... protection diodes at their gates.

> Since the amplifier would be discrete, we could
> limit the drain-source current using large resistors (100K+) and keep
> the user safe.

Why not construct the 1st amplifier stage with discrete components
to get hi-impedance and low noise ?
(However do not know enough about analog design to do that...)

> Noise would not be that important if the system
> averages the measurement over perhaps 100ms.

I thought more of the additional noise from the protection circuit that could
affect the EEG-measurement...

> A high overcurrent

Through the test subject ?

> would
> trigger the shut-off circuitry faster than an overcurrent that is
> only a little bit over the limit.

I have no idea, what IEC601-1 says how long the
current limits may be exceeded.


Regards,

Joerg




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--- In buildcheapeeg@y..., "Joerg Hansmann" <info@j...> wrote:
> Hi,
>
> here is a new protection circuit that limits user current
> to about 5uA if a worst case input stage failure occurs
> (inputs internally shorted to supply rails).

Hi Joerg,

it looks very nice! You've solved the problem!

But... :-)

You've only measured DC-impedance, and unfortunately we don't get
those fabulous numbers for AC.

So in the specifications we'll have to write:

Input impedance: It depends.

:-)

It will probably work quite nicely anyway, but perhaps not with
INA114 - it would be too noisy.

Regards,

Andreas

--- In buildcheapeeg@y..., "Jim Meissner" <jpmeissner@m...> wrote:

Hi Jim,

> Dear Joerg and Group:
>
> I have been following the Input Protection discussion, and in my
> opinion it is going in the wrong direction with the relays, etc.
>
> The FIRST consideration should be for the patient safety rather
[...]
> The SECOND consideration should be for the input amp.  You have
[...]
> The THIRD requirement of dealing with a catastrophic failure of the
> op amp, is in my opinion a mute point.  If you properly clamp the
> transients and protect the op amp inputs, it is not likely to fail.

Thanks for your input. This means we can put that part behind us.
The reason why it may sound like we've ignored mains isolation is
because that it is so easy to do.

So, boiling it down:

* ESD protection (using transistors)
* optoisolation, preferrably not using a regular optocoupler but more
of a transmitter/receiver design.
* battery operation

is necessary and sufficient?

>  Build something!

Working on it ...

/Andreas

Here's what I've been working on for a while. It still
needs a lot of adjustments. A surface-mount PCB-design
for the current schematic is 90% done - it fits in
less than 1/2 a euro-board. Don't expect the
through-hole version to be that small.

The LT1012 design got put on hold a bit - its only
advantage was that it can use larger resistors at the
inputs (though not large enough).

Please read the design notes on the schematic and
comment on what I've done so far.

Various stuff:

It runs on four 1.5V batteries.
It uses a LED for data transmission into a plastic
fiber. I've posted a schematic for the receiver
previously.
I've cut away everything non essential, so forget
about expandability...

/Andreas

_____________________________________________________
Do You Yahoo!?
se.yahoo.com

Andreas,

Now you're speaking my language, the language of tiny,
low power, unobtrusiveness. I want the whole EEG on my
thumbnail, but then I want my whole system on my thumb
nail (freaky thing is: it's getting close).

> fits in less than 1/2 a euro-board. Don't expect the
> through-hole version to be that small.

Sounds awesome, but hard to build.

> It runs on four 1.5V batteries.

Assuming I already have regulated 5V from another
supply (PT6302A) ... can I use that? My battery will
be 12V, powering an embedded PC through 3A 5V
switching regulator.

> I've cut away everything non essential, so forget
> about expandability...

Here's an idea. Leave two pins on the Uc set up for
TTL serial to another uC. A second board can grab
temp, gsr, ekg, emc, and sent data to the other uC
over TTL serial. The first uC just sends the data
down the line to the PC. A simple protocol can show
the data source (do we have this in the protocol in
use now?). The second uC (multi-parameter data
acquisition module) can also accept commands from
the first to set modes etc. A little command language
similar to what GPS receivers use could be set up
to program the modules from the PC. For example you
send an escape code sequence followed by a letter
and number combination. This could set the sampling
rates and other tweaks. I've done this before with
a single microcontroller connected to GPS, humidity,
barometer, and up to 256 1-wire temp sensors. The
PC protocol can be programmed in software, but also
works in a terminal session like hyperterminal or
minicom. Press you escape code, cay CTL-S for the
sampling rate then 300 then a termination char and
the system configures for that rate. The other
channels for temp, gsr, etc can be done the same
way, and can be shut off or on when desired.

   -- Doug

PS. Please proto the TinyEEG to make sure it works.
     I want this one! I may strugle with making the
     board, but it will be worth it.